AMOLED Array Substrate Through Hole Angle Control
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Solution Overview
Problem
In the manufacturing process of active-matrix organic light emitting diode (AMOLED) panels, the source/drain layer connected through an interlayer hole often becomes thin or broken due to an excessively large taper angle of the hole.
Innovation Solution
An array substrate is designed with a low temperature polysilicon layer, an inorganic film group layer having a through hole with a controlled angle between the sidewall and bottom wall, and a source/drain layer that covers and connects to the polysilicon layer, ensuring the angle is between 100 to 110 degrees to prevent thinning or breaking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the taper angle of the interlayer hole is reduced to prevent source/drain layer thinning or breaking, then the source/drain layer integrity is improved, but the manufacturing precision requirement increases
Solution Approach 1:
The patent changes the geometric parameter of the through hole from a conventional large taper angle to a specific small taper angle range (100-110 degrees between sidewall and bottom wall). This parameter modification directly prevents the source/drain layer from becoming thin or broken while maintaining electrical connectivity, resolving the contradiction between reliability and manufacturing precision by establishing a controlled angular parameter that balances both requirements.
2Strength
If the total thickness of the inorganic film group layer is reduced to less than 740 nm, then the through hole depth is reduced improving source/drain layer thickness, but the insulating performance may be compromised
Solution Approach 1:
The patent modifies the thickness parameter of the inorganic film group layer to a specific range (total thickness less than 740 nm, with individual layer thicknesses specified: first gate insulating layer less than 130 nm, second gate insulating layer less than 110 nm, interlayer dielectric layer less than 500 nm). This controlled reduction in thickness decreases the through hole depth, preventing source/drain layer thinning while maintaining adequate insulating performance through optimized layer composition and thickness distribution.
Data Source
AI summary
The present disclosure relates to an array substrate, a manufacturing method thereof, and a display panel, the array substrate including: a substrate, and a low temperature polysilicon layer, an inorganic film group layer, and a source/drain layer disposed on the substrate in sequence. The substrate includes a display region, the low temperature polysilicon layer located at the display region, the inorganic film group layer provided with a through hole, and an angle between a sidewall and a bottom wall of the through hole is not less than 100 degrees; the source/drain layer covering the sidewall and the bottom wall of the through hole to be connected to the low temperature polysilicon layer.