CMP Hard Mask Removal via Amorphous Carbon Barrier
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Solution Overview
Problem
In semiconductor device manufacturing, conventional chemical mechanical polishing (CMP) processes lead to over-polishing of polysilicon gates and excessive etching of interlayer dielectric layers, resulting in reduced transistor heights and compromised device performance and yield.
Innovation Solution
A method involving a dual hard mask layer structure, where a first amorphous carbon or silicon-based hard mask layer is used beneath a titanium nitride second hard mask layer, allowing for selective removal using a reactive gas mixture of hydrogen and nitrogen to prevent damage to the interlayer dielectric layer, thereby maintaining transistor heights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If over-etching is performed to completely remove hard mask on P-type aluminum gate transistor region, then hard mask removal is complete, but interlayer dielectric layer is unduly etched causing thickness loss
Solution Approach 1:
The patent introduces an amorphous carbon layer as an intermediary protective layer between the hard mask and the interlayer dielectric layer. During the etching process to remove the hard mask, this carbon layer acts as a sacrificial barrier that prevents the etchant from attacking the interlayer dielectric layer, thus allowing complete hard mask removal without dielectric layer damage.
Solution Approach 2:
The amorphous carbon layer is deposited beforehand to provide a protective cushion during the subsequent etching process. This pre-deposited layer absorbs the excessive etching that would otherwise damage the interlayer dielectric, enabling complete hard mask removal while preserving dielectric layer integrity.
2Ease of manufacture
If loss of thickness in interlayer dielectric layer occurs during hard mask removal, then hard mask is completely removed, but transistor height is reduced requiring additional polishing
Solution Approach 1:
The amorphous carbon layer serves as an intermediary protective barrier during hard mask removal, preventing thickness loss in the interlayer dielectric layer. By protecting the dielectric layer from over-etching, the transistor height is maintained without requiring additional compensatory polishing steps.
Solution Approach 2:
The pre-deposited amorphous carbon layer provides beforehand cushioning that prevents dielectric layer thickness loss during hard mask removal, thereby maintaining transistor height and eliminating the need for additional polishing to compensate for height loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents undue etching of interlayer dielectric layers and maintains the height of polysilicon gates, enhancing the performance and yield of semiconductor devices by precise control of the CMP process.
Implementation Method 1
removing the first hard mask layer using a reactive gas that is not susceptible to cause damage to the dielectric layer
Implementation Method 2
The aluminum gate chemical mechanical polishing (CMP) process is a very important process for manufacturing high-k metal gate transistors
Data Source
AI summary
A method for manufacturing a semiconductor device includes providing a substrate, a dielectric layer on the substrate, a first hard mask layer on the substrate, and a second hard mask layer on the first hard mask layer. The method also includes removing the first hard mask layer using a reactive gas that does not cause damage to the dielectric layer to improve the performance and yield of the semiconductor device.