Transistor TRIZ Cases

Isolation-region recesses add epitaxial source/drain volume in FinFETs, lowering contact resistance while limiting fin loss and short-channel effects.

A GaN sense transistor and two-stage sampling circuit deliver fast, lossless current feedback for accurate overcurrent and short-circuit protection.

A cut-metal-gate opening electrically separates adjacent FinFET gate stacks to limit shorting, leakage, and scaling-related fabrication risk.

A conditional restart delay stops undervoltage-induced toggling, cutting switch heating while preserving fast reactivation after brief faults.

Selective hydrogen diffusion raises source/drain conductivity in mixed semiconductor stacks while keeping the channel comparatively less conductive.

Overlapping gate and capacitor electrodes raise gate-drain capacitance, cutting ESD trigger voltage without adding external capacitor area.

Using two insulating materials in the isolation region reduces thermal degradation and crack defects in narrow semiconductor active regions.

Pre-formed pad openings and an insulator-surrounded pad structure prevent under etching, improving semiconductor fabrication yield and reliability.

Full-depletion FinFETs in a stacked sensor substrate cut thickness and parasitic capacitance, enabling finer contacts and smaller imaging devices.

A buried-region photodetector layout moves the depletion region deeper to improve near-infrared photon detection and timing resolution.

A nitrogen-rich oxynitride barrier at the fin interface blocks impurity diffusion, preserving channel composition, yield, and transistor reliability.

A two-part source/drain contact around a 2D channel increases contact area, lowers resistance, and preserves carrier mobility in short-channel transistors.

Homoepitaxial MBE growth on high-resistance β-Ga2O3 substrates avoids sapphire mismatch, suppresses re-evaporation, and raises film quality.

By moving capacitance into a vertical FEOL fin structure, this case reduces BEOL RC delay and footprint limits in stacked CMOS image sensors.

A voided dummy fin between active FinFETs reduces pattern loading and parasitic capacitance while improving electrical isolation.

Flat opposing gate conductors cut inductance and parasitic current, stabilizing wide-bandgap switch gate voltage at high temperature.

Oxygen radical treatment enriches the gate insulator interface, reducing contact resistance and electrical variation in oxide TFT LCDs.

A carbon hardmask patterns different gate workfunctions for non-planar I/O and logic transistors on one substrate without extra masks.

Two-step recess etching in FDSOI forms raised source/drains that cut parasitic resistance while limiting substrate cracking.

A layered oxide-semiconductor memory stores data without power by combining fast access with low leakage, avoiding refresh and high-voltage writing.

Orthogonal shallow and deep photoelectric regions share transfer paths to raise saturation charge while preserving two pupil division directions.

High-k gate insulation on a conformal SiGe gate trench maintains MOS capacitance at smaller nodes while reducing leakage current.

Covalent bonding between TMD channel layers and metallic contacts cuts contact resistance and supports denser fin-based transistor layouts.

Low-Ge Si/SiGe stacks are condensed after channel release to limit lattice mismatch and boost p-channel GAA FET performance.

A self-aligned wavy contact uses selective SiAs etching to protect epitaxial source/drain regions while increasing contact area and lowering resistance.

Shared electrode openings connect stacked transistors in OLED pixels, cutting pixel area while preserving reliable connections and resolution.

Layered polysilicon over a metal gate enables complete FUSI silicidation in HKMG MOSFETs while limiting hump defects and thickness non-uniformity.

Epitaxial core-shell channel regions induce strain and tune bandgap in GAA FETs, boosting carrier mobility, switching speed, and drive current.

A high-k and flowable oxide stack fills fin gaps, prevents fin bending, reduces seams and voids, and lowers RC delay.

Dielectric S/D spacers limit epitaxial growth to prevent fin-to-fin merging, while back-side contacts cut area, interconnects, and power use.

A multilayer pixel and holding circuit layout enables global shutter imaging and focus detection while reducing second-substrate circuit area.

Curved isolation layer sidewalls in stacked nanosheet transistors reduce short-channel effects and parasitic capacitance to improve reliability.

A boosting signal raises floating diffusion potential to improve charge transfer, image quality, and dynamic range across varying illuminance.

Switch-based overvoltage isolation protects ADC ICs in EX areas, enabling hot-swapping and accurate measurement without large resistors.

Raised spacer remnants between fins shift source/drain merge height, cutting gate-drain capacitance and RC delay for faster switching.

A titanium glue layer deposited by chemical vapor deposition ensures uniform coverage on contact hole inner surfaces for reliable copper plug formation.

A laterally diffused metal-oxide-semiconductor device integrates a Schottky diode with a specific contact structure to achieve ultra-low forward voltage drop.

A non-planar transistor body uses selective oxidation to create variable active semiconductor regions for flexible channel width control.

A semiconductor device design with a separate source electrode for the sense transistor, electrically isolated from the power transistor.

Simultaneous oxidation of polysilicon electrodes and silicon substrates consolidates processing steps, improving transistor uniformity and productivity.

A semiconductor process implants dopants simultaneously in LDMOS, resistor, and BJT regions to reduce dedicated photolithographic steps.

HfO2 or TiO2 charge trapping layers capture stray charges to minimize interference between adjacent word lines in scaled DRAM arrays.

Wrapping a metal contact around epitaxial layers reduces contact resistance and size while eliminating the silicide manufacturing process.

Stacking-type capacitive elements with grid-like electrodes resolve the contradiction between high capacitance and small planar area in semiconductor devices.

A parasitic vertical PNP bipolar transistor uses shallow trench isolation and ion implantation to form collector, base, and emitter regions.

A display apparatus adjusts gate power voltage levels across writing and holding frames to optimize driving efficiency.

Vertical gate-all-around transistors arranged in a hexagonal lattice reduce manufacturing costs while maintaining data retention.

A self-aligned contact method replaces dielectric lines with metal to ensure precise electrical connections.

A bonding pad structure uses a conductive buffer layer to directly contact the metal pad.

A MOSFET structure incorporating a back gate and counter doped region to adjust threshold voltage via applied bias.

Semiconductor structure blocks minority carriers from photoelectric conversion portions using a dual potential barrier.

Conformal spacer deposition defines critical dimensions, resolving lithographic precision limits during aggressive pitch scaling.

A fabrication method creates silicided gates alongside non-silicided source drain regions using a blocking layer.

A single-slope comparison device generates multiple crossings by globally applying an offset to the pixel signal during analog-to-digital conversion.

Back-irradiation solid-state imaging devices separate photodiodes from transistors to resolve low sensitivity and complex manufacturing constraints.

Programmable electrical connections disconnect individual trench capacitors to compensate for process variations and achieve precise capacitance values.

Dummy trenches expose base layer sidewalls for hole discharge, enabling narrower mesa widths and lower on-voltage without sacrificing latch-up tolerance.

Extending a semiconductor layer from the substrate to pillar sidewalls prevents floating body effects and reduces coupling capacitance between buried bit lines.

A parasitic PIN device formed on a silicon substrate using shallow trench isolation oxide layers and N-type pseudo buried layers.

Retrograde well structure distributes charge carriers in drain extended field effect transistors.

Oxygen-donating bilayer spacer passivates vacancies in high-k dielectrics to reduce pFET threshold voltage increases from thermal processing.

Differentiated peripheral doping broadens the driving range to reduce leakage current and improve grayscale control.

A buried insulator layer under a collector region depletes lateral charge to increase breakdown voltage in silicon-on-insulator transistors.

Placing a current limiting resistor on the MOS bulk terminal isolates ESD protection from the signal path, preventing heat generation during normal operation.

A nitride spacer protects the oxide layer between control and floating gate electrodes during oxidation.

A gate trench insulating film combines thermal oxidation and deposition layers to enhance voltage resistance in semiconductor devices.

Multi-layer source electrodes prevent metal ion dissolution into liquid crystal layers, maintaining voltage holding rates in scanning antennas.

Dynamic switching of snapback and non-snapback diverting elements prevents overvoltage damage while minimizing semiconductor chip area.

A ferroelectric material layer in non-volatile memory uses negative capacitance to amplify internal voltage.

An intermediary metal layer transfers laser-generated heat to adjacent inorganic structures, preventing direct exposure and reducing thermal degradation.

An N-type ring structure blocks parasitic leakage paths under shallow trench isolation, increasing breakdown voltage from 8 V to 15.5 V.

A semiconductor device uses a charge trap layer to adjust threshold voltage via electron trapping.

Segmented gate structure prevents high temperature deformation and misalignment, enhancing carrier mobility and reliability.

Crossed spacer patterning simplifies DRAM capacitor fabrication by enabling accurate high aspect ratio through holes without complex in-situ etching steps.

Hollow region under channel concentrates film stress to boost carrier mobility while reducing ON resistance and OFF capacitance.

Alternating large and small ligand precursors resolve gap-fill contradictions in high-aspect-ratio trenches without additional etching.

An outer first adhesive with hydrophilic treatment suppresses electrochemical migration in silver wiring without adding expensive barrier layers.

A charge trap memory device uses a composite of charge trapping and insulating nanoparticles to enhance retention.

Spatially varying hafnium-indium-zinc-oxide composition suppresses environmental sensitivity and thermal instability while maintaining high carrier mobility.

A FinFET gate structure uses segmented TiAl and TiN work function metal layers to define distinct n-type and p-type device characteristics.

A stacked MOS electrostatic discharge circuit uses RC biasing to trigger NMOS devices and create low-ohmic current paths.

Matching the metal gate electrode vertical profile at the end cap to the active region reduces parasitic capacitance among gate stacks.

A pixel feedback circuit with a capacitive element positioned near the semiconductor substrate reduces signal interference.

Modified semiconductor regions with higher charge carrier recombination rates create depletion zones that cancel unwanted harmonics in multi-frequency switches.