Transistor TRIZ Cases

Isolation-region recesses add epitaxial source/drain volume in FinFETs, lowering contact resistance while limiting fin loss and short-channel effects.

A GaN sense transistor and two-stage sampling circuit deliver fast, lossless current feedback for accurate overcurrent and short-circuit protection.

A cut-metal-gate opening electrically separates adjacent FinFET gate stacks to limit shorting, leakage, and scaling-related fabrication risk.

A conditional restart delay stops undervoltage-induced toggling, cutting switch heating while preserving fast reactivation after brief faults.

Selective hydrogen diffusion raises source/drain conductivity in mixed semiconductor stacks while keeping the channel comparatively less conductive.

Overlapping gate and capacitor electrodes raise gate-drain capacitance, cutting ESD trigger voltage without adding external capacitor area.

Using two insulating materials in the isolation region reduces thermal degradation and crack defects in narrow semiconductor active regions.

Pre-formed pad openings and an insulator-surrounded pad structure prevent under etching, improving semiconductor fabrication yield and reliability.

Full-depletion FinFETs in a stacked sensor substrate cut thickness and parasitic capacitance, enabling finer contacts and smaller imaging devices.

A buried-region photodetector layout moves the depletion region deeper to improve near-infrared photon detection and timing resolution.

A nitrogen-rich oxynitride barrier at the fin interface blocks impurity diffusion, preserving channel composition, yield, and transistor reliability.

A two-part source/drain contact around a 2D channel increases contact area, lowers resistance, and preserves carrier mobility in short-channel transistors.

Homoepitaxial MBE growth on high-resistance β-Ga2O3 substrates avoids sapphire mismatch, suppresses re-evaporation, and raises film quality.

By moving capacitance into a vertical FEOL fin structure, this case reduces BEOL RC delay and footprint limits in stacked CMOS image sensors.

A voided dummy fin between active FinFETs reduces pattern loading and parasitic capacitance while improving electrical isolation.

Flat opposing gate conductors cut inductance and parasitic current, stabilizing wide-bandgap switch gate voltage at high temperature.

Oxygen radical treatment enriches the gate insulator interface, reducing contact resistance and electrical variation in oxide TFT LCDs.

A carbon hardmask patterns different gate workfunctions for non-planar I/O and logic transistors on one substrate without extra masks.

Two-step recess etching in FDSOI forms raised source/drains that cut parasitic resistance while limiting substrate cracking.

A layered oxide-semiconductor memory stores data without power by combining fast access with low leakage, avoiding refresh and high-voltage writing.

Orthogonal shallow and deep photoelectric regions share transfer paths to raise saturation charge while preserving two pupil division directions.

High-k gate insulation on a conformal SiGe gate trench maintains MOS capacitance at smaller nodes while reducing leakage current.

Covalent bonding between TMD channel layers and metallic contacts cuts contact resistance and supports denser fin-based transistor layouts.

Low-Ge Si/SiGe stacks are condensed after channel release to limit lattice mismatch and boost p-channel GAA FET performance.

A self-aligned wavy contact uses selective SiAs etching to protect epitaxial source/drain regions while increasing contact area and lowering resistance.

Shared electrode openings connect stacked transistors in OLED pixels, cutting pixel area while preserving reliable connections and resolution.

Layered polysilicon over a metal gate enables complete FUSI silicidation in HKMG MOSFETs while limiting hump defects and thickness non-uniformity.

Epitaxial core-shell channel regions induce strain and tune bandgap in GAA FETs, boosting carrier mobility, switching speed, and drive current.

A high-k and flowable oxide stack fills fin gaps, prevents fin bending, reduces seams and voids, and lowers RC delay.

Dielectric S/D spacers limit epitaxial growth to prevent fin-to-fin merging, while back-side contacts cut area, interconnects, and power use.

A multilayer pixel and holding circuit layout enables global shutter imaging and focus detection while reducing second-substrate circuit area.

Curved isolation layer sidewalls in stacked nanosheet transistors reduce short-channel effects and parasitic capacitance to improve reliability.

A boosting signal raises floating diffusion potential to improve charge transfer, image quality, and dynamic range across varying illuminance.

Switch-based overvoltage isolation protects ADC ICs in EX areas, enabling hot-swapping and accurate measurement without large resistors.

Raised spacer remnants between fins shift source/drain merge height, cutting gate-drain capacitance and RC delay for faster switching.