Dual-Gate Memory Device Electrical Shielding
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Solution Overview
Problem
Dual-gate semiconductor memory devices face challenges with strong electrical interaction between memory and non-memory devices, leading to read disturb and program disturb issues, as well as inefficiencies in programming and reading operations due to the need for high voltages and uniform charge distribution across crystalline silicon channels.
Innovation Solution
A dual-gate memory device structure is developed with a sensitivity parameter less than a predetermined value, allowing for electrical shielding between memory and non-memory devices, using a composite gate dielectric layer and polycrystalline semiconductor material, where one gate dielectric layer stores electric charge to minimize interaction and optimize programming and reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a dual-gate structure with crystalline silicon channel is used to achieve strong electrical interaction between memory and non-memory devices, then read capability is improved, but read disturb and program disturb increase
Solution Approach 1:
The patent changes the material parameter from crystalline silicon to amorphous silicon, which fundamentally alters the electrical interaction characteristics. Amorphous silicon provides weaker electrical interaction between the memory and non-memory devices, reducing the harmful electrical coupling that causes read and program disturb, while still allowing the dual-gate structure to function for read operations.
Solution Approach 2:
The patent applies different material qualities to different regions: the channel region uses amorphous silicon with specific electrical properties that provide localized electrical shielding, while the gate dielectric regions maintain their charge storage functionality. This local differentiation allows the channel to shield against harmful electrical interaction while preserving read capability through controlled electrical coupling.
2Manufacturing precision
If crystalline silicon channel material is used to ensure uniform charge distribution, then manufacturing precision is improved, but sensitivity to electrical interaction increases
Solution Approach 1:
The patent changes the material parameter from crystalline silicon to amorphous silicon, which has different electrical properties that reduce sensitivity to electrical interaction while still allowing for controlled charge distribution. The amorphous silicon's disordered atomic structure provides natural electrical shielding that reduces the harmful effects of strong electrical coupling between devices.
3Reliability
If high voltages are applied to achieve programming and reading operations, then operation reliability is improved, but energy consumption increases
Solution Approach 1:
The patent changes the material properties from crystalline to amorphous silicon, which modifies the electrical interaction characteristics to reduce the strength of coupling between memory and non-memory devices. This reduction in electrical interaction strength allows programming and reading operations to be performed with lower voltages, thereby reducing energy consumption while maintaining operational reliability through the controlled electrical shielding effect.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution minimizes charge disturbs during programming and reading, enabling high-density memory circuits with reduced program and read pass voltage requirements, thereby improving the reliability and efficiency of NAND-type non-volatile memory devices.
Implementation Method 1
a gate dielectric layer formed over the gate electrode and having a composite structure including a first dielectric layer and a second dielectric layer... electric charge can be stored either between the first gate electrode and the semiconductor layer, or between the second gate electrode and the semiconductor layer
Implementation Method 2
A dual-gate memory device structure is developed with a sensitivity parameter less than a predetermined value, allowing for electrical shielding between memory and non-memory devices
Data Source
AI summary
A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that a sensitivity parameter relating an electrical interaction between the gate electrodes of the access device and the memory device is less than a predetermined value. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices.