Surround Gate DRAM Pillars Mitigating Floating Body Effect
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices face challenges in reducing the floating body effect, especially in high-capacity, high-speed applications with small-scale processes, where surrounding gate transistors can exhaust charges and require higher integration.
Innovation Solution
A method of fabricating a memory device involving the formation of pillars with epitaxial layers, a trench structure, and specific insulating and conductive layers to minimize the floating body effect, including a node dielectric layer, common bottom electrode, and gate structures, which reduces the area occupied by the memory device and lowers current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If surrounding gate transistors are used to increase memory cell density, then memory capacity is improved, but floating body effect increases causing charge exhaustion in off-mode
Solution Approach 1:
The gate structure is segmented into multiple gates surrounding the channel from different directions (top, bottom, and sidewalls), creating a surround gate configuration. This segmentation allows better control of the channel and reduces the floating body effect by providing multiple pathways for charge control, thereby improving reliability while maintaining high memory cell density.
Solution Approach 2:
The gate structure transitions from a planar 2D configuration to a 3D surround gate configuration that envelops the channel from multiple dimensions. This dimensional change enables the gate to control the channel from top, bottom, and sidewalls, effectively reducing the floating body effect while increasing memory cell density through better space utilization.
2Area of moving object
If device size is reduced to increase integration, then memory capacity is improved, but floating body effect becomes more pronounced
Solution Approach 1:
The invention transitions from planar 2D transistors to 3D surround gate structures, utilizing vertical and lateral dimensions to control the channel. This dimensional change allows effective reduction of floating body effect in miniaturized devices by providing omnidirectional gate control, enabling continued scaling while maintaining reliability.
Solution Approach 2:
The gate control parameters are changed by introducing multiple gates at different positions and orientations around the channel. This parameter change in the gate configuration provides enhanced electrostatic control over the channel, effectively suppressing the floating body effect even as device dimensions are reduced for higher integration.
3Ease of manufacture
If conventional transistor structures are used, then manufacturing is simpler, but memory cell density is lower
Solution Approach 1:
The transistor structure is segmented into multiple gates and regions, creating a surround gate configuration that increases memory cell density. While more complex than conventional structures, the segmentation follows systematic fabrication processes that build upon existing manufacturing capabilities, achieving higher density through structured complexity.
Solution Approach 2:
The gate structures are nested around the channel region, with multiple gates positioned at different levels and orientations. This nesting configuration maximizes the use of available space, allowing higher memory cell density while following a structured approach that can be integrated into existing manufacturing flows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively decreases the floating body effect, reduces current leakage, and is suitable for small-scale processes like the 55 nm process, enhancing the performance and capacity of DRAM devices while maintaining high-speed performance.
Implementation Method 1
Each pillar has a plurality of epitaxial layers
Data Source
AI summary
A memory device is disclosed. A substrate is provided. A plurality of pillars is disposed on the substrate. Each pillar has a plurality of epitaxial layers, has a first sidewall and a second sidewall. A trench is formed between the pillars. A common bottom electrode is disposed in a lower portion of the trench and surrounded by a node dielectric layer. A first insulating layer is disposed on the common bottom electrode inside the trench. A plurality of gate structures is disposed on the first sidewall and inside the trench. A second insulating layer is disposed inside the trench and adjacent to the gate structures. A third insulating layer, body line, and fourth insulating layer are respectively disposed on the substrate and located between the second insulating layer and the second sidewall.