Bi-layer Interfacial Layer for High-k Metal Gate Mobility
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Solution Overview
Problem
High-k metal gate stacks in semiconductor devices face challenges such as carrier mobility degradation due to the diffusion of dopant materials and Fermi-level pinning effects, which affect threshold voltage stability and channel performance in sub-micron transistors.
Innovation Solution
A bi-layer interfacial layer structure comprising a nitrogen-rich first dielectric layer and a nitrogen-deficient, oxygen-rich second dielectric layer is used, with a high-k dielectric layer and a metal gate conductor layer, where work function adjusting dopant species like lanthanum are diffused within the high-k dielectric and second dielectric layer, keeping them away from the semiconductor substrate to maintain threshold voltage reduction and inversion thickness scaling without degrading carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dopant material is diffused into the gate dielectric to adjust work function, then threshold voltage is reduced, but carrier mobility degrades due to dopant diffusion into the channel
Solution Approach 1:
The interfacial layer is divided into two distinct layers: a nitrogen-rich first layer adjacent to the semiconductor substrate and a nitrogen-deficient, oxygen-rich second layer adjacent to the high-k dielectric layer. This segmentation creates a barrier that prevents dopant species from diffusing into the channel while allowing work function adjustment in the second layer, thereby resolving the contradiction between threshold voltage control and carrier mobility preservation.
Solution Approach 2:
The nitrogen-rich first dielectric layer acts as an intermediary barrier between the dopant species in the second layer and the semiconductor substrate. This intermediate layer prevents harmful dopant diffusion into the channel while allowing the second layer to perform its work function adjustment function, thus maintaining both threshold voltage stability and carrier mobility.
2Productivity
If metal gate is used to eliminate polysilicon depletion effect, then channel performance improves, but Fermi-level pinning effect causes high threshold voltage
Solution Approach 1:
The patent changes the chemical composition parameters of the interfacial layer by creating a bi-layer structure with different nitrogen and oxygen concentrations. The nitrogen-deficient, oxygen-rich second layer specifically engineered at the high-k dielectric interface modifies the work function and reduces Fermi-level pinning effects, thereby adjusting threshold voltage while maintaining the metal gate's channel performance benefits.
3Manufacturing precision
If dopant species are kept away from the channel to maintain carrier mobility, then threshold voltage reduction is compromised
Solution Approach 1:
The patent utilizes the vertical dimension by creating a stratified bi-layer interfacial structure where the nitrogen-deficient, oxygen-rich second layer is positioned between the high-k dielectric and the nitrogen-rich first layer. This vertical arrangement allows dopant species to be concentrated in the second layer for work function adjustment while the first layer provides a barrier, achieving both threshold voltage reduction and carrier mobility maintenance through spatial separation in the vertical dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces threshold voltage and maintains inversion thickness scaling while improving carrier mobility by keeping the dopant species away from the channel, thus enhancing the performance of high-k metal gate stacks in semiconductor devices.
Implementation Method 1
the nitrogen rich first dielectric layer serves to separate the work function adjusting dopant species from the semiconductor substrate surface
Implementation Method 2
work function adjusting dopant species diffused within the high-k dielectric layer and within the nitrogen deficient, oxygen rich second dielectric layer
Data Source
AI summary
A gate stack structure for field effect transistor (FET) devices includes a nitrogen rich first dielectric layer formed over a semiconductor substrate surface; a nitrogen deficient, oxygen rich second dielectric layer formed on the nitrogen rich first dielectric layer, the first and second dielectric layers forming, in combination, a bi-layer interfacial layer; a high-k dielectric layer formed over the bi-layer interfacial layer; a metal gate conductor layer formed over the high-k dielectric layer; and a work function adjusting dopant species diffused within the high-k dielectric layer and within the nitrogen deficient, oxygen rich second dielectric layer, and wherein the nitrogen rich first dielectric layer serves to separate the work function adjusting dopant species from the semiconductor substrate surface.