Non-Planar I/O and Logic Transistors With Split Workfunction Gates
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face challenges in optimizing the performance of non-planar I/O and logic transistors on common substrates, as they often rely on a single workfunction for all devices, limiting independent control over device performance and requiring additional mask operations to differentiate between different types of transistors.
Innovation Solution
The approach involves using a carbon hardmask to selectively etch and pattern different workfunction metal layers for I/O and logic transistors on a common substrate, allowing for independent control of each device's performance without additional mask operations by exploiting the etch rate dependence between different feature sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single workfunction is used for all transistors on a common substrate, then manufacturing process simplicity is maintained, but independent control over device performance is limited
Solution Approach 1:
The patent applies local quality by depositing different workfunction metal layers (e.g., titanium nitride for I/O transistors, tungsten for logic transistors) in specific regions of the substrate. This allows each transistor type to have locally optimized workfunction values tailored to their performance requirements, enabling independent control over device characteristics while maintaining a common substrate architecture.
Solution Approach 2:
The manufacturing process is segmented into separate workfunction metal deposition steps for different transistor regions. By dividing the workfunction assignment into distinct stages with region-specific material deposition, the patent enables differentiated workfunctions for I/O and logic transistors without requiring complete process rework, thus managing complexity through structured segmentation.
2Adaptability or versatility
If additional mask operations are used to differentiate workfunctions, then device performance control is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent employs preliminary action by using self-aligned deposition techniques where workfunction metal layers are deposited in a predetermined sequence. The first workfunction metal layer is deposited across the entire substrate, then a second workfunction metal layer is deposited only in specific regions using self-alignment to the gate structures. This preliminary, self-aligned approach eliminates the need for additional photolithography mask operations, reducing manufacturing complexity while achieving differentiated workfunctions.
Solution Approach 2:
The patent introduces an intermediary approach by using a self-aligned mask formed from the gate structure itself as the deposition template. This intermediary element (the gate structure serving as its own mask) enables precise spatial control of workfunction metal deposition without requiring external photolithography masks, thereby simplifying the manufacturing process while maintaining the ability to differentiate workfunctions.
3Quantity of substance
If transistor dimensions are scaled down to increase density, then capacity is improved, but process constraints become overwhelming
Solution Approach 1:
The patent applies parameter changes by varying the workfunction metal layer thickness and composition as key parameters to optimize device performance at scaled dimensions. By adjusting these material parameters rather than relying solely on geometric scaling, the patent maintains process feasibility and performance control even as transistor dimensions are reduced to increase device density on the substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the fabrication of non-planar semiconductor devices with distinct workfunctions for I/O and logic transistors, enhancing performance targeting without the need for extra mask operations, thereby improving the efficiency and flexibility of semiconductor device fabrication.
Implementation Method 1
exploiting the etch rate dependence between different feature sizes
Data Source
AI summary
Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.