Multi-Layer Inverter Chain Fabrication via Vertical Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor device fabrication techniques face challenges in efficiently connecting multiple inverter structures across multiple layers to form a functional inverter chain, which is crucial for digital logic applications like ring oscillators, due to limitations in inter-layer connection methods and material integration processes.
Innovation Solution
The method involves forming a semiconductor structure with multiple device layers, where each layer includes inverter structures connected in cascade through specific inter-layer connection structures, utilizing techniques such as photolithography, etching, and annealing to create precise electrical connections between the inverter structures across layers, ensuring effective signal propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional single-layer fabrication techniques are used to connect inverter structures, then the fabrication process is simpler, but the signal transmission efficiency and reliability deteriorate due to limited inter-layer connection methods
Solution Approach 1:
The patent transitions from traditional single-layer planar connections to multi-layer three-dimensional vertical connections. Inter-layer connection structures (via holes and conductive plugs) are formed to establish electrical pathways between device layers stacked vertically, enabling efficient signal transmission across multiple layers while maintaining compact footprint and improving reliability through redundant connection paths.
2Productivity
If multiple inter-layer connection structures are formed to connect inverter structures across layers, then the signal transmission improves, but the manufacturing precision requirements increase due to alignment challenges
Solution Approach 1:
Alignment marks are formed on the substrate before depositing the first device layer. These pre-formed marks serve as reference features for subsequent photolithography and etching steps, enabling precise alignment of inter-layer connection structures across multiple fabrication stages. This preliminary positioning action ensures that via holes and conductive plugs align correctly with underlying transistor terminals despite process variations.
3Manufacturing precision
If advanced photolithography and etching techniques are used to create precise inter-layer connections, then the connection accuracy improves, but the fabrication time and process complexity increase
Solution Approach 1:
The fabrication process is divided into distinct modular stages: forming alignment marks, depositing first device layer with transistors, creating via holes through dielectric layers, forming conductive plugs, depositing second device layer, and establishing final inter-layer connections. Each stage is optimized independently with specific photolithography and etching parameters, allowing parallel processing and reducing overall fabrication cycle time while maintaining high precision through controlled sequential steps.
Data Source
AI summary
Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and one or more inter-layer connection structures. The first device layer is formed on a substrate and includes one or more first inverter structures. The second device layer is formed on the first device layer and includes one or more second inverter structures. The one or more inter-layer connection structures are configured to electrically connect to the first inverter structures and the second inverter structures.