FinFET Leakage Reduction via Localized Insulating Layer
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Solution Overview
Problem
Fin field effect transistors experience increased gate induced drain leakage (GIDL) and junction leakage, leading to reduced retention time in dynamic random access memory (DRAM) due to the higher leakage currents compared to conventional planar transistors.
Innovation Solution
A semiconductor device with a fin field effect transistor design that includes a silicon substrate, active patterns, isolation layer patterns, gate electrodes, impurity regions, and contact plugs, where the contact plugs are formed using polysilicon with varying impurity concentrations to reduce contact resistance and leakage, and an insulating layer pattern is used under the impurity regions to minimize junction leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fin field effect transistor is used to increase integration degree and control channel region, then device capacity and channel control are improved, but gate induced drain leakage and junction leakage increase
Solution Approach 1:
The patent applies local quality by forming an insulating layer pattern specifically at the drain region of the fin field effect transistor. This insulating layer is localized where the highest leakage occurs (at the drain junction), providing targeted leakage suppression without affecting other device regions. The insulating material is deposited conformally on the sidewalls and upper surface of the fin structure, creating a localized barrier that reduces GIDL and junction leakage while maintaining the high-capacity benefits of the fin structure.
2Productivity
If a fin field effect transistor is used to increase integration degree, then device capacity is improved, but retention time is reduced due to increased leakage
Solution Approach 1:
The insulating layer pattern is strategically positioned at the drain region where leakage current originates. By applying the insulating material conformally on the fin sidewalls and upper surface, the patent creates a localized protection zone that suppresses both GIDL and junction leakage. This localized approach effectively reduces total leakage current, thereby extending retention time in DRAM applications while preserving the high integration density enabled by the fin structure.
3Reliability
If contact plugs are formed to make contact with impurity regions, then electrical connection is improved, but contact resistance may increase
Solution Approach 1:
The insulating layer pattern serves as an intermediary structure that indirectly benefits contact resistance by reducing leakage currents in the drain region. By suppressing GIDL and junction leakage, the insulating layer ensures that more current flows through the intended conduction paths via the contact plugs and impurity regions, effectively improving the signal-to-leakage ratio and maintaining low contact resistance despite the presence of the insulating barrier.
Data Source
AI summary
In a fin field effect transistor (Fin FET) and a method of manufacturing the Fin FET, the Fin FET includes an active pattern inside which insulating layer patterns are formed, an isolation layer pattern enclosing a sidewall of the active pattern such that an opening exposing a sidewall of the active pattern located between the insulating layer patterns is formed, a gate electrode formed on the active pattern to fill the opening, impurity regions formed at portions of the active pattern adjacent to sidewalls of the gate electrode, an insulating interlayer covering the active pattern and the gate electrode and contact plugs formed through portions of the insulating interlayer and the active pattern adjacent to the sidewalls of the gate electrode such that the contact plug makes contact with the impurity region.