FDSOI Source/Drain Recess Etching for Lower Parasitic Resistance
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, reducing minimum feature sizes leads to increased parasitic resistance and manufacturing defects such as substrate cracking due to coefficient of thermal expansion mismatch between silicon layers, which affects the integration density and electrical performance of transistors.
Innovation Solution
The formation of fully depleted silicon on insulator (FDSOI) transistors with raised source/drain regions, where the top silicon layer is etched to create deeper recesses using a fluorine-ozone mixture process, reducing parasitic resistance and supporting subsequent processing steps while maintaining a sufficient thickness to prevent substrate cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the top silicon layer is etched deeper to reduce parasitic resistance, then electrical performance is improved, but the risk of substrate cracking increases due to CTE mismatch
Solution Approach 1:
The patent applies local quality by creating a non-uniform thickness profile in the top silicon layer. The layer is thinned selectively in the channel region to enable deeper source/drain recesses for reduced parasitic resistance, while maintaining sufficient thickness at the edges and under the recesses to prevent substrate cracking. This localized variation in thickness allows simultaneous optimization of electrical performance and mechanical reliability.
Solution Approach 2:
The patent employs beforehand cushioning by maintaining a residual silicon layer (10-50 Å) beneath the source/drain recesses before final etching. This residual layer acts as a cushion that absorbs thermal stress and prevents cracking during subsequent processing steps and device operation. The cushioning layer is removed only after it has served its protective function, allowing deeper recesses to be formed safely.
2Productivity
If the minimum feature size is reduced to increase integration density, then more components can be integrated, but parasitic resistance increases
Solution Approach 1:
The patent addresses the parasitic resistance issue by transitioning from a two-dimensional planar structure to a three-dimensional vertical structure. By etching deeper source/drain recesses into the silicon layer and forming raised source/drain regions, the current path is extended vertically, providing additional conduction pathways that compensate for the reduced lateral dimensions. This dimensional transition allows integration density to increase while parasitic resistance is controlled through the enhanced vertical current flow.
3Reliability
If the top silicon layer is thinned to enable deeper source/drain recesses, then parasitic resistance is reduced, but mechanical support for overlying features is compromised
Solution Approach 1:
The patent applies local quality by creating spatial variation in silicon layer thickness. The layer is thinned selectively in the channel region to allow deeper source/drain recesses for reduced parasitic resistance, while maintaining sufficient thickness (10-50 Å) in other regions, particularly under the recesses and at the edges, to provide mechanical support for overlying gate and insulator structures. This localized thickness control simultaneously achieves electrical performance and mechanical stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrical performance by reducing parasitic resistance and minimizing manufacturing defects, allowing for improved integration density and faster switching speeds in transistors.
Implementation Method 1
the top silicon layer may be etched to define source/drain recesses using a fluorine-ozone mixture (FOM) process
Implementation Method 2
etching the oxide region using diluted hydrogen fluoride (dHF)
Implementation Method 3
forming an oxide region in the top semiconductor layer, the oxide region being on sidewalls and a bottom surface of the recess
Data Source
AI summary
A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.