Nanosheet FET Angular Indent Spacer for Gate CD Scaling

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Solution Overview

Problem

Current semiconductor device fabrication methods face challenges in achieving uniformity and scalability in nanosheet field effect transistors (FETs) due to limitations in gate critical dimension (CD) scaling and contact resistance, particularly in maintaining effective length (Leff) and extension variation control.

Innovation Solution

The method involves forming nanosheet stacks with alternating sacrificial and active semiconductor layers, creating angular indents in the sacrificial layers, filling these with a low-κ material, and forming gate metal layers in the spaces left by the sacrificial layers' removal, using self-limiting etching techniques to ensure uniformity and allow for gate CD scaling without sacrificing device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional planar FET fabrication methods are used, then manufacturing simplicity is maintained, but device density and channel control are insufficient

Engineering Contradiction:
Improvedevice densityVSAvoidfabrication process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The channel region is segmented into multiple stacked nanosheets instead of a single planar channel, increasing effective channel width and device density while maintaining fabrication compatibility through sequential layer formation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The device architecture transitions from two-dimensional planar structure to three-dimensional stacked nanosheet structure, enabling increased device density and improved gate control without proportionally increasing footprint area

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Length of moving object

If gate CD scaling is pursued to reduce device footprint, then device density increases, but uniformity and contact resistance control deteriorate

Engineering Contradiction:
Improvegate critical dimensionVSAvoiduniformity and contact resistance control
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

Angular indents are formed in the sacrificial layers before gate deposition, pre-defining the gate footprint and enabling uniform gate CD scaling across the wafer while maintaining precise control over gate length and contact alignment

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The sacrificial layers incorporate angular indents with specific geometries that create localized regions for optimized gate contact and uniform spacing, ensuring consistent electrical properties across different device regions

Inventive Principle:
Principle #3Local quality

3Reliability

If effective length Leff and extension variation control are improved, then device performance increases, but fabrication complexity and process difficulty increase

Engineering Contradiction:
Improveeffective length controlVSAvoidfabrication process ease
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The sacrificial layers with angular indents self-align during deposition processes, automatically defining gate positions and effective lengths without requiring additional alignment steps or complex process control

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The angular indent geometry parameters (angles, depths, spacing) are optimized to naturally produce the desired effective length and extension characteristics, converting complex dimensional control into geometric parameter control

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances top-to-bottom and across-wafer uniformity, enables effective gate CD scaling, and allows for further device pitch scaling without compromising channel electrostatics or contact resistance, improving the manufacturing of nanosheet FETs.

Implementation Method 1

filling these with a low-κ material layer

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Data Source

PatentUS11348999B2Nanosheet semiconductor devices with sigma shaped inner spacer
Publication Date: 2022.05.31 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11348999B2 patent drawing
  • US11348999B2 patent drawing
  • US11348999B2 patent drawing

AI summary

A method of manufacturing a nanosheet field effect transistor (FET) device is provided. The method includes forming a plurality of nanosheet stacks on a substrate, the nanosheet stacks including alternating layers of sacrificial layers and active semiconductor layers. The method includes removing portions of the sacrificial layers to form angular indents in each side thereof, then filling the indents with a low-κ material layer. The method further includes forming source drain regions between the nanosheet stacks, removing remaining portions of the sacrificial layers, and then forming gate metal layers in spaces formed by the removal of the sacrificial layers.