Metal Gate Stack Isolation Layout for Scaled FinFET Reliability
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at smaller sizes due to increased complexity and difficulty in fabrication processes as feature sizes decrease, leading to issues with processing and manufacturing complexity.
Innovation Solution
The process involves forming FinFET structures with patterned fins using photolithography and self-aligned processes, followed by the formation of dummy gate stacks, metal gate stacks, and a cut-metal-gate opening to separate the gate stacks, ensuring electrical isolation and preventing short circuiting through precise etching and deposition techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The gate structure is segmented into multiple metal layers (first metal gate layer, second metal gate layer) with different work functions, allowing independent optimization of threshold voltage and drive current. The source/drain regions are segmented into selective doped regions (n-type and p-type) to enable independent control of carrier injection. This segmentation resolves the contradiction by allowing complex device performance requirements to be met through layered structure rather than requiring further miniaturization.
Solution Approach 2:
Different regions of the device are assigned different material properties and doping types to optimize local functions. The first metal gate layer has one work function tailored for n-type transistor control, while the second metal gate layer has another work function for p-type transistor control. The source/drain regions have selective doping (n-type in first region, p-type in second region) to optimize carrier injection locally. This local quality approach allows high performance without requiring further size reduction.
2Area of stationary object
If feature sizes decrease to increase functional density, then chip area utilization is improved, but manufacturing reliability deteriorates
Solution Approach 1:
Dummy gate stacks are formed preliminarily before the actual metal gate deposition process. These dummy gates serve as placeholders that define the gate region geometry early in the process, allowing subsequent self-aligned deposition of metal layers and source/drain regions. This preliminary action ensures precise dimensional control and alignment without requiring tighter process tolerances at smaller feature sizes, thereby maintaining manufacturing reliability while achieving high area utilization.
Solution Approach 2:
The dummy gate stacks act as intermediary structures that mediate between the photolithography patterning step and the final metal gate formation. They provide a stable reference structure that enables self-aligned processes to achieve precise positioning without directly requiring sub-10nm lithography resolution. This intermediary approach maintains manufacturing reliability by using larger, more controllable intermediate structures rather than attempting to directly pattern the final small-scale features.
3Length of moving object
If conventional gate structures are used at smaller sizes, then device scaling is achieved, but short circuiting and current leakage increase
Solution Approach 1:
The gate structure uses composite materials with different work functions arranged in layers. The first metal gate layer and second metal gate layer have different work function values, creating a composite gate structure that provides both strong n-type and p-type transistor control. This composite structure prevents short circuiting and current leakage by ensuring proper potential barriers at each interface, even at scaled dimensions where conventional single-material gates would fail.
Solution Approach 2:
The solution transitions from a conventional two-dimensional planar gate to a three-dimensional multi-layer gate structure. By adding the vertical dimension with multiple metal layers stacked above each other, the device achieves better electrostatic control and potential barrier management without further reducing the lateral footprint. This dimensional change allows scaling while preventing leakage through enhanced vertical field control.
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first metal gate stack and a second metal gate stack over the semiconductor substrate. The first metal gate stack and the second metal gate stack are electrically isolated from each other, and the first metal gate stack has a curved edge facing the second metal gate stack. The semiconductor device structure also includes a dielectric layer surrounding the first metal gate stack and the second metal gate stack.