Charge Trap Memory Nanoparticle Composite Leakage Control

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Solution Overview

Problem

In charge trap memory devices, the increased density of nanoparticles leads to higher leakage currents and agglomeration issues, which reduce information retention time and memory performance.

Innovation Solution

A charge trap memory device using a composite of charge trapping nanoparticles and insulating nanoparticles, where the nanoparticles are capped with a surfactant in a liquid synthesis process using an organic solvent to prevent agglomeration and control the distance between nanoparticles, thereby reducing leakage currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the density of nanoparticles is increased to improve memory capacity, then the memory capacity and integration density are improved, but the leakage current increases and information retention time decreases

Engineering Contradiction:
Improvenanoparticle densityVSAvoidinformation retention time
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

An insulating layer is introduced as an intermediary between charge trapping nanoparticles to prevent direct tunneling interactions. This mediator reduces leakage current between densely packed nanoparticles while maintaining high nanoparticle density for improved memory capacity and integration density.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent uses a composite structure combining charge trapping nanoparticles with insulating materials. This composite approach allows high nanoparticle density for capacity while the insulating component suppresses leakage current, resolving the contradiction between density and retention time.

Inventive Principle:
Principle #40Composite materials

2Quantity of substance

If the density of nanoparticles is increased to improve integration density, then the integration density is improved, but nanoparticle agglomeration occurs and memory performance deteriorates

Engineering Contradiction:
Improvenanoparticle densityVSAvoidnanoparticle agglomeration control
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The insulating layer serves as a physical spacer and barrier between nanoparticles, preventing agglomeration during manufacturing processes. This intermediary maintains nanoparticle dispersion at high densities while facilitating easier manufacturing control.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The insulating layer provides localized separation between nanoparticles, creating different functional zones: charge trapping regions with high nanoparticle density and insulating regions that prevent agglomeration. This local quality differentiation enables high integration density without manufacturing difficulties.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The composite approach enhances memory performance by maintaining charge retention and preventing nanoparticle agglomeration, leading to improved memory characteristics and longer information retention times.

Implementation Method 1

the charge trapping nanoparticles and the insulating nanoparticles in the composite solution may be capped with a surfactant by a liquid synthesis process using an organic solvent to allow the charge trapping nanoparticles and the insulating nanoparticles to be miscible together

Methodology Applied
Scientific EffectSurfactant: Surfactant

Implementation Method 2

as the density of nanoparticles increases, the distance between the nanoparticles becomes shorter, thereby increasing a leakage current to the tunneling between the nanoparticles

Methodology Applied
Scientific EffectTunneling:

Data Source

PatentUS7482619B2Charge trap memory device comprising composite of nanoparticles and method of fabricating the charge trap memory device
Publication Date: 2009.01.27 SAMSUNG ELECTRONICS CO LTD
  • US7482619B2 patent drawing
  • US7482619B2 patent drawing
  • US7482619B2 patent drawing

AI summary

Provided are a charge trap memory device including a substrate and a gate structure including a charge trapping layer formed of a composite of nanoparticles, and a method of manufacturing the charge trap memory device.