Wavy Source/Drain Contact Profile for Lower-Resistance FinFETs
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Solution Overview
Problem
Conventional FinFET fabrication techniques face challenges in protecting epitaxial source/drain features from damage during the source/drain contact etching process, leading to limited contact area and increased resistance.
Innovation Solution
The use of a top layer of silicon arsenide (SiAs) or other pentavalent silicon compounds in epitaxial source/drain features, which provides anisotropic etching selectivity, allowing for a self-aligned wavy contact profile that reduces source/drain resistance and mitigates damage during etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional source/drain contact etching process is used, then the etching process can be completed, but the epitaxial source/drain features are damaged or lost and the contact area is limited
Solution Approach 1:
The patent applies local quality by creating a multi-layer source/drain structure where the top layer has different etching selectivity than the lower epitaxial layers. This allows the etch process to selectively remove the top layer while preserving the underlying epitaxial source/drain features, thereby maintaining their integrity while enabling adequate contact area formation
Solution Approach 2:
The top layer acts as an intermediary that protects the underlying epitaxial source/drain features during the contact etching process. By introducing this intermediate layer with distinct etching properties, the patent enables selective etching that spares the sensitive epitaxial layers while still allowing contact formation
2Ease of manufacture
If conventional contact etching is performed, then the process can proceed, but the contact resistance increases due to limited contact area
Solution Approach 1:
The patent utilizes vertical dimensionality by creating a multi-layer structure with different etching selectivities. This allows the contact etch to penetrate through the top layer and form adequate contact area with the underlying epitaxial layers, thereby reducing contact resistance while maintaining ease of manufacture through selective etching processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of semiconductor devices by reducing contact resistance and improving the integrity of epitaxial source/drain features during the etching process.
Implementation Method 1
The lower epitaxial layer includes a wavy top surface. A contact is directly formed over the wavy top surface of the lower epitaxial layer of the source/drain feature. In some embodiments, the top epitaxial layer includes a pentavalent silicon compound different than a material of the lower epitaxial layer and provides anisotropic etching selectivity with respect to the lower epitaxial layer.
Data Source
AI summary
A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.