Metal Gate Electrode Profile Matching for Parasitic Capacitance Reduction
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Solution Overview
Problem
As semiconductor devices are scaled down, it becomes challenging to prevent parasitic capacitance among gate stacks due to reduced spacing, affecting device performance in CMOS fabrication.
Innovation Solution
A method of fabricating semiconductor devices involves forming gate stacks with metal gates, using a 'gate last' process, and employing techniques like atomic layer deposition for high-k dielectric layers and chemical vapor deposition for gate electrodes, along with spacer formation and removal processes to manage parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If gate length and spacing between devices are decreased to scale down semiconductor devices, then device integration density is improved, but parasitic capacitance among gate stacks increases affecting device performance
Solution Approach 1:
The patent removes the conventional polysilicon gate electrode material and replaces it with a metal gate electrode. This extraction of the problematic polysilicon material eliminates the parasitic capacitance issue while maintaining the gate's functional properties through the use of metal materials with different electrical characteristics.
Solution Approach 2:
The patent changes the material parameter of the gate electrode from polysilicon to metal, fundamentally altering the electrical properties of the gate structure. This parameter change reduces parasitic capacitance while enabling continued scaling of gate dimensions and spacing.
2Reliability
If a gate last process is used to replace polysilicon gate with metal gate, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the high-k dielectric layer and metal gate electrode structure before final gate patterning. The metal gate electrode is deposited and patterned in advance, and the gate last process systematically replaces polysilicon gate formation steps with metal gate formation steps, improving device performance while managing manufacturing complexity through structured process integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance, enhances device operation speed, and minimizes the likelihood of breakdown and failure, while allowing for efficient integration of metal gates in CMOS technology.
Implementation Method 1
employing techniques like atomic layer deposition for high-k dielectric layers
Implementation Method 2
chemical vapor deposition for gate electrodes
Data Source
AI summary
A semiconductor device comprises a non-conductive gate feature over a substrate, and a metal gate electrode over the substrate. The metal gate electrode comprises a portion over an active region of the substrate, and a portion over an isolation feature of the substrate ending at an end cap. A vertical profile of the metal gate electrode at the end cap matches a vertical profile of the metal gate electrode in the portion over the active region.