Display Apparatus Gate Driver Voltage Control
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Solution Overview
Problem
Display panel drivers face challenges in reducing power consumption, especially when operating in low frequency modes, as the gate power voltage remains at a direct-current level, limiting power reduction.
Innovation Solution
The display apparatus employs a low frequency driving mode with distinct voltage levels for gate signals and emission signals in writing and holding frames, utilizing a combination of polysilicon and oxide thin film transistors to optimize power consumption, and includes a driving controller with level shifters and voltage generators to manage these signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the driving frequency of the display panel is reduced to reduce power consumption, then energy consumption decreases, but the gate power voltage remains at a direct-current level which limits further power reduction
Solution Approach 1:
The gate power voltage is transformed from a static direct-current level to a dynamic alternating signal that switches between high and low levels according to the driving frequency. This dynamic adjustment allows the voltage to adapt to different operating modes (writing frame and holding frame), enabling further power consumption reduction beyond what frequency reduction alone could achieve
Solution Approach 2:
The gate power voltage parameters are changed from a fixed DC level to a time-varying alternating signal with different high and low levels. This parameter transformation allows the system to optimize power consumption by applying appropriate voltage levels at different time periods, directly addressing the limitation of static DC voltage in low-frequency driving modes
2Use of energy by moving object
If the gate power voltage is reduced in holding frames to save power, then energy efficiency improves, but the complexity of voltage management increases
Solution Approach 1:
The gate power voltage is applied periodically with distinct high and low levels corresponding to writing frames and holding frames. This periodic structure simplifies voltage management by creating a predictable, rhythmic pattern that can be controlled through timing signals, reducing the complexity compared to arbitrary voltage adjustments while still achieving significant power savings during holding frames
Solution Approach 2:
The system prepares and applies different gate power voltage levels in advance for writing frames and holding frames. By pre-establishing the voltage schedule based on the driving frequency and frame type, the system simplifies real-time voltage management while ensuring optimal power consumption at each stage of the display operation cycle
Data Source
AI summary
A display apparatus includes a display panel, a first gate driver, a second gate driver, a third gate driver, and a data driver. The display apparatus is operable in a low frequency driving mode, and the low frequency driving mode includes a writing frame and a holding frame. At least one of gate power voltages used to generate a first gate signal, a second gate signal, and an emission signal has a first voltage level in the writing frame of the low frequency driving mode and a second voltage level in the holding frame of the low frequency driving mode. The data voltage is applied to the pixel in the writing frame of the low frequency driving mode. The data voltage applied to the pixel in the writing frame of the low frequency driving mode is maintained in the holding frame of the low frequency driving mode.