CMOS Transistor Metal Gate Diffusion Barrier
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
CMOS transistors face issues with parasitic capacitance due to impurity ion diffusion in poly-Si gates, leading to degraded current drivability and threshold voltage deviations, and metal gates reacting with gate electrodes, affecting semiconductor module and processor-based system electrical properties.
Innovation Solution
The implementation of CMOS transistors with interconnection structures featuring insulating, diffusion stopping, work-function adjusting, and power applying materials stacked sequentially, with different diffusion stopping material structures to prevent atom diffusion and stabilize threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a poly-Si gate is used to control the CMOS transistor, then the work function can be determined along with the semiconductor substrate, but parasitic capacitance is generated due to impurity ion diffusion, degrading current drivability
Solution Approach 1:
The patent extracts and removes the problematic poly-Si gate material from the structure, replacing it with a metal gate that does not generate parasitic capacitance. This eliminates the source of the harmful effect while maintaining the gate's essential function of controlling current flow between source and drain regions.
Solution Approach 2:
The patent changes the material parameter of the gate from poly-Si to metal, fundamentally altering the electrical characteristics. This parameter change eliminates parasitic capacitance generation while allowing precise control of work function through the metal gate's inherent properties and interface engineering.
2Object-generated harmful factors
If a metal gate is used to replace the poly-Si gate to prevent parasitic capacitance, then parasitic capacitance is eliminated, but the metal gate reacts with the gate electrode and diffuses constituent atoms into the diffusion stopping pattern and gate insulating pattern, causing threshold voltage deviation
Solution Approach 1:
The patent introduces an intermediary diffusion stopping pattern positioned between the metal gate and the gate insulating pattern. This intermediary layer prevents direct contact and atomic diffusion between the metal gate and other structures, eliminating the harmful reaction while allowing the metal gate to maintain its low parasitic capacitance advantage.
Solution Approach 2:
The patent segments the gate structure into distinct functional layers: metal gate, diffusion stopping pattern, and gate insulating pattern. This segmentation isolates the metal gate from reactive components, preventing atomic diffusion and threshold voltage deviation while maintaining the benefits of metal gate technology.
3Reliability
If the gate structure includes multiple stacked layers (gate insulating pattern, poly-Si gate, metal gate) to control electrical properties, then work function and threshold voltage can be controlled, but the structure complexity increases and manufacturing difficulty rises
Solution Approach 1:
The patent designs the diffusion stopping pattern to serve multiple functions simultaneously: preventing atomic diffusion from the metal gate, providing an interface layer for work function control, and maintaining structural integrity. This multi-functionality reduces the need for separate dedicated layers, simplifying the overall structure while maintaining electrical property control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the electrical properties of CMOS transistors by preventing atom diffusion and stabilizing threshold voltage, thereby improving the performance of semiconductor devices and modules within processor-based systems.
Implementation Method 1
a gate structure including a gate insulating pattern, a metal gate and a diffusion stopping pattern that are sequentially stacked, the diffusion stopping pattern preventing diffusion of constituent atoms of a gate electrode
Implementation Method 2
The gate structure controls the flow of charge between source and drain regions of a CMOS transistor
Data Source
AI summary
Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.