Stacked MOS ESD Circuit with RC Biasing for Low-Impedance Protection
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Solution Overview
Problem
Integrated circuits are susceptible to damage from electrostatic discharge (ESD), which can lead to reliability issues and device failure, as existing ESD protection circuits may not adequately prevent damage during normal operation and low-voltage events.
Innovation Solution
A stacked MOS ESD protection circuit utilizing RC circuits to bias and trigger NMOS devices, creating a conductive path between supply nodes during ESD events while preventing device degradation by keeping gate voltages within safe limits during normal operation, using capacitors and resistors to manage voltage and trigger timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If stacked MOS clamping devices are used for ESD protection, then device destruction from momentary high voltage is prevented, but device susceptibility to ESD damage and reliability problems increase due to inadequate protection during normal operation
Solution Approach 1:
The ESD protection circuit dynamically transitions between high-impedance state during normal operation and low-impedance state during ESD events. The circuit remains inactive during normal operation to avoid interfering with circuit functionality, then rapidly activates when ESD voltage exceeds the breakdown voltage to provide protection, and finally resets to high-impedance state after the ESD event concludes.
Solution Approach 2:
The circuit proactively prevents device degradation by maintaining high-impedance state during normal operation, thereby avoiding any potential interference with normal circuit functionality. This preliminary protective measure ensures the protection circuit does not cause reliability issues before an ESD event actually occurs.
2Object-affected harmful factors
If stacked MOS power clamps are used in multiple power domains, then supply nodes and I/O pins are protected from high voltage, but device complexity increases with multiple power domains
Solution Approach 1:
The ESD protection circuit is segmented into distinct high-impedance and low-impedance states, allowing independent control for different power domains. Each power domain can be protected individually through dedicated ESD protection circuits, enabling modular protection architecture that scales with system complexity without proportionally increasing overall device complexity.
3Object-affected harmful factors
If ESD protection circuits are activated during normal operation, then continuous protection is provided, but device degradation occurs due to constant conduction
Solution Approach 1:
The ESD protection circuit operates periodically rather than continuously, transitioning between active protection state and inactive high-impedance state. The circuit activates only when ESD voltage exceeds the breakdown threshold, provides protection during the ESD event duration, then resets to inactive state, creating a periodic on-off operation pattern that prevents continuous conduction and associated device degradation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively protects integrated circuits from ESD by ensuring low-ohmic current paths during ESD events while maintaining device integrity during normal operation, with optimized performance parameters and reduced risk of oscillation or device degradation.
Implementation Method 1
a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node
Implementation Method 2
a first resistor coupled between the gate of the first MOS device the intermediate node, and a second resistor coupled between the gate of the second MOS device and the second node
Implementation Method 3
electrostatic discharge (ESD) is the transfer of an electrostatic charge between bodies at different electrostatic potentials or voltages
Implementation Method 4
creating a conductive path between supply nodes during ESD events
Data Source
AI summary
In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.