MIS Capacitor on Finned Semiconductor Structure
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Solution Overview
Problem
The challenge in the fabrication of integrated circuits is the effective formation of metal-insulator-semiconductor (MIS) capacitors on finned semiconductor structures, particularly in FinFET devices, where existing methods struggle to enhance capacitance while maintaining small dimensions and reducing costs.
Innovation Solution
A method involving the formation of a monolithic structure with a semiconductor substrate and parallel semiconductor fins, where a doped layer with a specific conductivity type is created beneath the fins, and a capacitor dielectric layer is directly applied on the fins and substrate, followed by a metal layer that extends into the spaces between the fins, forming a metal-insulator-semiconductor capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional capacitor formation methods are used on finned structures, then the fabrication process is simpler, but the capacitance is insufficient and the capacitor area is large
Solution Approach 1:
The patent transitions from planar capacitor formation to three-dimensional capacitor formation by utilizing the vertical fin structures. The capacitor dielectric layer is formed conformally on the sidewalls and top surfaces of the fins, creating capacitance in the vertical dimension rather than only in the planar dimension. This allows achieving higher capacitance within a smaller footprint area.
Solution Approach 2:
The capacitor structure is nested within the finned semiconductor structure. The capacitor dielectric layer is deposited conformally on the fin surfaces, and the conductive layer is formed within the spaces between fins, effectively nesting the capacitor formation process within the existing fin architecture rather than requiring separate dedicated capacitor regions.
2Ease of manufacture
If MIS capacitors are integrated with FinFETs on the same substrate, then costs are reduced and area is saved, but the fabrication process complexity increases
Solution Approach 1:
The fin structures serve dual purposes: they function as the active channel regions for FinFET devices and simultaneously serve as the electrode structures for MIS capacitors. The same fin structures that enable high-performance transistors also provide the necessary surface area and geometry for forming high-capacitance capacitors, eliminating the need for separate dedicated capacitor regions.
Solution Approach 2:
The capacitor dielectric layer is formed conformally on the fin surfaces during the same fabrication sequence used to define the FinFET structures. The preliminary formation of fins with appropriate geometry and doping creates the substrate for subsequent capacitor formation, allowing both device types to be integrated without requiring separate processing stages.
3Reliability
If the metal layer extends into the spaces between fins, then capacitance is enhanced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes changes in material properties and deposition parameters to achieve conformal coverage. By controlling the dielectric material deposition parameters (such as atomic layer deposition conditions), the process automatically adapts to the three-dimensional fin geometry, ensuring uniform thickness on vertical sidewalls and horizontal surfaces without requiring ultra-precise positioning.
Solution Approach 2:
The conformal deposition process is self-aligning to the fin structures. The dielectric layer automatically conforms to the existing fin geometry and extends into the spaces between fins, with the fin structures themselves defining the boundaries and patterns for the capacitor formation without requiring additional lithographic patterning steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the capacitance of on-chip capacitors, reduces the capacitor area, and lowers costs by effectively integrating MIS capacitors with FinFETs on the same substrate, improving the electrical characteristics and efficiency of integrated circuits.
Implementation Method 1
forming a capacitor dielectric layer directly on the fins and the top surface region of the substrate
Implementation Method 2
forming a metal layer on the capacitor dielectric layer
Implementation Method 3
The fins and a top surface region of the substrate are doped in a first region of the substrate over the first doped layer such that they have a second conductivity type opposite from the first conductivity type and the doped top surface region of the substrate is electrically connected to the doped fins
Data Source
AI summary
MIS capacitors are formed using a finned semiconductor structure. A highly doped region including the fins is formed within the structure and forms one plate of a MIS capacitor. A metal layer forms a second capacitor plate that is separated from the first plate by a high-k capacitor dielectric layer formed directly on the highly doped fins. Contacts are electrically connected to the capacitor plates. A highly doped implantation layer having a conductivity type opposite to that of the highly doped region provides electrical isolation within the structure.