Capacitor Fabrication via Crossed Spacer Patterning for High Aspect Ratio Holes

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Solution Overview

Problem

The fabrication of capacitors in dynamic random access memory (DRAM) involves complex steps for creating high aspect ratio through holes, which complicates the manufacturing process as chip sizes decrease.

Innovation Solution

A method is developed that involves forming spacers along two different directions using tri-layer structures on etching stop layers, allowing for accurate transfer of patterns to a sacrificial layer with high etching selectivity, thereby simplifying the formation of through holes with high aspect ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If traditional methods are used to fabricate through holes with high aspect ratio, then the capacitors can be formed in reduced chip area, but the manufacturing steps become quite complicated

Engineering Contradiction:
Improvechip areaVSAvoidfabrication steps
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The method performs preliminary patterning actions by forming spacers in multiple directions (first spacers, second spacers, third spacers) before the actual through-hole etching. These spacers are formed in advance to define the through-hole positions and patterns, eliminating the need for complex in-situ patterning during the etching process itself. The spacers serve as pre-prepared masks that guide the subsequent etching steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The fabrication process is segmented into distinct stages: first forming spacers in a first direction, then forming additional spacers in second and third directions, and finally using these combined spacer structures as masks for etching. This segmentation allows each spacer formation step to be independently optimized and simplifies the overall process control compared to attempting to create the complete pattern in a single step.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If high etching selectivity ratio is achieved between pattern and sacrificial layer, then pattern transfer accuracy improves, but the number of material layers increases

Engineering Contradiction:
Improvepattern transfer accuracyVSAvoidlayer structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent introduces an intermediate pattern transfer layer between the spacers and the sacrificial layer. This intermediate layer acts as a mediator that receives the pattern from the spacers and transfers it to the sacrificial layer during etching. The high etching selectivity between this intermediate layer and the sacrificial layer ensures accurate pattern transfer, while the intermediate layer protects the spacers from direct etching damage.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The structure employs composite material stacking with different etching selectivities: spacers made of one material, an intermediate pattern transfer layer made of another material with high etching selectivity difference relative to the sacrificial layer. This composite structure allows selective etching of the intermediate layer and sacrificial layer while preserving the spacer pattern, achieving high pattern transfer accuracy.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enables the accurate formation of high aspect ratio through holes while reducing the complexity of the fabrication steps, improving the efficiency of capacitor manufacturing.

Implementation Method 1

a first etching process using the organic pattern and the first spacers as a mask is performed to etch the first etching stop layer and remove the second etching stop layer

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS10204911B2Method for fabricating capacitor
Publication Date: 2019.02.12 UNITED MICROELECTRONICS CORP
  • US10204911B2 patent drawing
  • US10204911B2 patent drawing
  • US10204911B2 patent drawing

AI summary

A method for fabricating a capacitor includes providing a substrate and a first etching stop layer on the substrate; forming a plurality of first spacers on the first etching stop layer; forming an organic layer and a second etching stop layer sequentially on the first spacers, the organic layer covering the first spacers; forming a plurality of second spacers on the second etching stop layer, each second spacer crossing the first spacers; transferring a pattern of the second spacers to the organic layer to form an organic pattern; performing an etching process using the organic pattern and the first spacers as a mask to form an etching stop pattern and remove the second etching stop layer; transferring the etching stop pattern to the substrate to form a plurality of through holes.