Vertical Transistor Body-Tied Structure Floating Body Effect
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor memory apparatuses, reducing the unit size of transistors is challenging due to the difficulty in fabricating vertical transistors with minimal area occupation, which affects productivity and leads to issues like floating body effects and increased coupling capacitance between buried bit lines.
Innovation Solution
A body-tied structure is implemented by extending a semiconductor layer from the substrate to the sidewalls of pillars, connecting them electrically, using SiGe or Si materials, and incorporating a buried insulating film to reduce coupling capacitance and prevent floating body effects, with a gate structure that has a straight upper portion and stepped lower portion not in contact with the semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a vertical transistor structure is used to reduce unit size, then area occupation is reduced, but floating body effects and increased coupling capacitance occur
Solution Approach 1:
A semiconductor layer is introduced as an intermediary element that extends from the substrate to the sidewalls of the vertical channel region. This intermediary structure provides electrical connection between the substrate and the vertical channel, eliminating the floating body effect while maintaining the compact vertical transistor geometry.
Solution Approach 2:
The patent transitions from a conventional planar transistor structure to a vertical three-dimensional structure. By extending the channel region vertically from the substrate surface, the transistor achieves smaller footprint area while the semiconductor layer provides lateral electrical connection to resolve the floating body issue in this new dimensional configuration.
2Area of stationary object
If a vertical transistor structure is used to reduce unit size, then area occupation is reduced, but coupling capacitance between buried bit lines increases
Solution Approach 1:
The semiconductor layer acts as a mediator that electrically connects the vertical channel to the substrate, providing a controlled electrical path that reduces unwanted capacitive coupling between adjacent buried bit lines while maintaining the vertical transistor's compact area.
3Ease of manufacture
If conventional horizontal transistors are used, then fabrication is simpler, but unit size occupation is larger
Solution Approach 1:
The patent employs vertical channel formation extending from the substrate surface upward, transforming the conventional two-dimensional planar transistor into a three-dimensional vertical structure. This dimensional change reduces the horizontal area occupation while the process steps remain adapted from conventional fabrication techniques.
Solution Approach 2:
The vertical transistor structure segments the channel region into distinct vertical zones with different doping profiles (first and second doped regions), allowing independent optimization of different channel sections while maintaining overall compactness and manufacturability.
Data Source
AI summary
A semiconductor device and a method for fabricating the same are provided to prevent a floating body effect and reduce coupling capacitance between buried bit lines. The semiconductor device comprises a first pillar disposed over a semiconductor substrate and including a vertical channel region, a bit line located in the lower portion of the vertical channel region inside the first pillar and a semiconductor layer extended from the semiconductor substrate to one sidewall of the first pillar.