Imaging Device Feedback Circuit Reduces kTC Noise

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Solution Overview

Problem

Current imaging devices face challenges in reducing kTC noise, particularly during the resetting process, which affects the quality of images captured.

Innovation Solution

The imaging device incorporates a feedback circuit with a capacitive element and a feedback transistor, where the feedback path is located closer to the semiconductor substrate than the signal line, and a second capacitor with a dielectric layer, to reduce coupling and noise interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a feedback circuit is provided to reduce kTC noise, then noise suppression is improved, but device complexity increases

Engineering Contradiction:
ImprovekTC noiseVSAvoidcircuit complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The feedback circuit is nested within the pixel structure, with the feedback transistor and capacitive element integrated into the existing pixel circuitry. The feedback path is positioned between the charge accumulation region and the signal line, utilizing the existing transistor and capacitor structures to provide noise suppression without adding significant external components.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The feedback path is positioned in a different spatial dimension (vertically between layers) rather than horizontally along the signal line. By placing the feedback transistor and capacitive element in a position closer to the semiconductor substrate than the signal line, the patent reduces coupling capacitance and noise interference while maintaining effective feedback functionality.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Object-affected harmful factors

If the feedback path is placed closer to the semiconductor substrate than the signal line, then coupling capacitance is reduced, but manufacturing precision requirements increase

Engineering Contradiction:
Improvecoupling capacitanceVSAvoidlayer alignment precision
Core Design Contradiction:
Object-affected harmful factorsVSManufacturing precision

Solution Approach 1:

The patent applies different spatial positioning strategies to different circuit elements. The feedback transistor and capacitive element are positioned in a specific vertical layer (closer to the substrate) that is distinct from the signal line layer. This localized positioning optimization reduces coupling capacitance in the feedback path while allowing other parts of the circuit to maintain standard manufacturing tolerances.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively suppresses kTC noise, enhancing image quality by minimizing noise interference and allowing for faster noise cancellation.

Implementation Method 1

a photoelectric converter generating signal charge by photoelectric conversion

Methodology Applied
Scientific EffectPhotoelectric conversion: Photoelectric Effect

Data Source

PatentUS11183524B2Imaging device and camera system
Publication Date: 2021.11.23 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO LTD
  • US11183524B2 patent drawing
  • US11183524B2 patent drawing
  • US11183524B2 patent drawing

AI summary

An imaging device including a semiconductor substrate; pixels arranged on the semiconductor substrate in a first direction; and a signal line extending in the first direction. Each of the pixels includes a photoelectric converter generating signal charge by photoelectric conversion, a charge accumulation region that accumulates the signal charge output from the photoelectric converter, a first transistor that outputs a signal to the signal line according to an amount of the signal charge accumulated in the charge accumulation region, a capacity circuit that is coupled to a gate of the first transistor and that includes a first capacitive element, the first capacitive element including a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, at least one of the first electrode and the second electrode containing a metal. The first capacitive element is closer to the semiconductor substrate than the signal line.