ESD Protection Circuit with Bulk Terminal Resistor for Source Drivers
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Solution Overview
Problem
Semiconductor chips face increased vulnerability to electrostatic discharge (ESD) due to shrinking circuit element dimensions, and current ESD protection methods using current limiting resistors generate heat, raising operating temperatures during normal operations.
Innovation Solution
An output circuit design for semiconductor chips that incorporates a switch and current limiting resistors coupled to the bulk terminals of MOS transistors, rather than on the output path, to provide ESD protection while minimizing power loss and heat generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a current limiting resistor is disposed on the output path to provide ESD protection, then ESD current is blocked or reduced, but heat energy is generated and operating temperature rises during normal operations
Solution Approach 1:
The patent segments the ESD protection function from the normal signal path by placing the current limiting resistor in a separate branch connected to the bulk terminal of the MOS transistor. This allows ESD protection to be provided independently without affecting the normal output signal path, thereby preventing heat generation during normal operations while maintaining ESD protection capability.
Solution Approach 2:
The bulk terminal of the MOS transistor serves as an intermediary element that provides a dedicated path for ESD current. By connecting the current limiting resistor to the bulk terminal rather than the output path, the patent creates an intermediate protection mechanism that isolates the ESD protection function from the normal signal transmission path.
2Speed
If circuit element dimensions are shrunk to submicron level to increase performance and operation speed, then performance and operation speed are improved, but ESD tolerance capability deteriorates
Solution Approach 1:
The patent applies local quality by providing enhanced ESD protection specifically at the bulk terminal of the MOS transistor, which is a critical local point for ESD current flow. By placing the current limiting resistor at this specific location rather than uniformly across the entire circuit, the patent provides targeted ESD protection that is effective for submicron devices without affecting overall circuit performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively limits ESD currents and prevents heat-related temperature increases, maintaining driving capability and reducing thermal energy production during normal operations.
Implementation Method 1
The first resistor is coupled between the bulk terminal of the first MOS transistor and a first power supply terminal
Implementation Method 2
data voltages for driving the display panel are transmitted from the output buffer to the output pad via the switch
Data Source
AI summary
The present invention provides an output circuit with electrostatic discharge (ESD) protection in a semiconductor chip of a source driver. The source driver is configured to drive a display panel. The output circuit includes an output buffer, an output pad, a switch and a first resistor. The switch is coupled between the output buffer and the output pad, wherein data voltages for driving the display panel are transmitted from the output buffer to the output pad via the switch. The switch includes a first metal oxide semiconductor (MOS) transistor, which includes a first terminal coupled to the output pad, a bulk terminal and a gate terminal. The first resistor is coupled between the bulk terminal of the first MOS transistor and a first power supply terminal.