Vertical TFTs for Memory Array Digit Line Coupling
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Solution Overview
Problem
Conventional DRAM memory arrays face challenges in achieving high-speed operation and efficient signal amplification due to the limitations of planar transistors in coupling local digit lines to hierarchical digit lines, which restricts the number of memory cells and increases space requirements.
Innovation Solution
The implementation of vertical thin film transistors (TFTs) between local digit lines and hierarchical digit lines allows for high-speed operation by reducing space requirements and enabling longer hierarchical digit lines, thereby supporting more local digit lines and memory cells, with vertical TFTs acting as multiplexing transistors to amplify signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If planar transistors are used to couple local digit lines to hierarchical digit lines, then the structure is simpler to manufacture, but the space requirements increase and operational speed decreases
Solution Approach 1:
The patent transitions from planar (2D) transistor architecture to vertical (3D) transistor architecture. The vertical TFTs extend in the vertical dimension, allowing current to flow from source through channel to drain in the vertical direction rather than laterally. This dimensional change enables higher density integration and reduces the horizontal space footprint while maintaining or improving electrical performance for high-speed operation.
Solution Approach 2:
The patent changes the structural parameters of the transistor from planar geometry to vertical geometry. This includes changing the channel orientation, source-drain configuration, and gate positioning. These parameter changes enable the transistor to achieve both compact footprint and high-speed performance by optimizing the electrical characteristics in the vertical configuration.
2Quantity of substance
If planar transistors are used for coupling digit lines, then manufacturing is easier, but the number of memory cells and hierarchical digit line length are limited
Solution Approach 1:
By moving to vertical transistors, the patent achieves higher integration density without proportionally increasing manufacturing complexity. The vertical architecture allows more memory cells to be packed into the same footprint by utilizing the vertical space, effectively increasing the quantity of memory cells while the manufacturing process remains relatively comparable to planar approaches.
3Area of stationary object
If vertical thin film transistors are used between digit lines, then space requirements are reduced and more memory cells can be supported, but the device structure becomes more complex
Solution Approach 1:
The vertical transistor structure utilizes the vertical dimension to reduce horizontal footprint. By orienting the channel, source, and drain vertically, the device achieves compact lateral dimensions while the internal structure complexity is managed through standardized vertical TFT fabrication techniques.
4Quantity of substance
If hierarchical digit lines are made longer to support more memory cells, then capacity increases, but signal amplification efficiency decreases
Solution Approach 1:
The vertical TFTs act as intermediate switching elements between local digit lines and hierarchical digit lines. These vertical transistors provide efficient signal coupling and amplification at each hierarchical level, enabling the system to support more memory cells with extended hierarchical digit lines while maintaining signal integrity and amplification efficiency through the vertical transistor's low-resistance vertical current path.
Data Source
AI summary
In the examples disclosed herein, a memory array can have a first group of memory cells coupled to a first digit line at a first level and a second group of memory cells coupled to a second digit line at the first level. A third digit line can be at a second level and can be coupled to a main sense amplifier. A first vertical thin film transistor (TFT) can be at a third level between the first and second levels can be coupled between the first digit line and the third digit line. A second vertical TFT can be at the third level and can be coupled between the second digit line and the third digit line. A local sense amplifier can be coupled to the first and second digit lines.