FinFET Source/Drain Spacer Profile for Lower Gate-Drain Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, the integration density of electronic components increases, but this leads to challenges such as increased gate-to-drain capacitance, RC delay, and reduced switching speed, which are not effectively addressed by existing technologies.
Innovation Solution
The formation of source/drain regions with reduced volume and cross-sectional area is achieved by depositing a spacer material over fins and etching it to create higher epitaxial growth points between fins, reducing the cross-sectional area of merged source/drain regions and minimizing gate-to-drain capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but forming source/drain regions with reduced volume and cross-sectional area becomes challenging
Solution Approach 1:
The source/drain region formation is divided into multiple stages: initial epitaxial growth to form a first portion, followed by selective removal to create recesses, and then controlled regrowth to form a second portion. This segmentation allows precise control over the final source/drain geometry, enabling reduced cross-sectional area while maintaining manufacturing feasibility.
Solution Approach 2:
A mandrel structure is formed beforehand to define the recess regions before epitaxial growth occurs. This preliminary action establishes the precise geometry needed for the source/drain regions, ensuring that the final structure achieves the required reduced volume and cross-sectional area with high manufacturing precision.
2Object-affected harmful factors
If source/drain region volume is reduced to lower gate-to-drain capacitance, then device speed improves, but manufacturing complexity increases
Solution Approach 1:
A mandrel structure serves as an intermediary tool to define the recess regions during source/drain formation. This mandrel enables precise control over the source/drain geometry without requiring complex direct patterning methods, thereby reducing manufacturing complexity while achieving the reduced volume needed to lower gate-to-drain capacitance.
Solution Approach 2:
The patent replaces complex mechanical patterning and etching processes with epitaxial growth methods. By using controlled epitaxial regrowth from the recesses, the source/drain regions are formed with precise geometry and reduced volume, simplifying the overall manufacturing process while achieving lower gate-to-drain capacitance.
3Loss of time
If source/drain region cross-sectional area is reduced to lower RC delay, then device speed improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent controls source/drain region geometry by changing epitaxial growth parameters: initial growth conditions create the first portion, selective removal defines recesses, and controlled regrowth conditions form the second portion with reduced cross-sectional area. These parameter changes enable precise geometric control to achieve lower RC delay while maintaining manufacturing precision.
Solution Approach 2:
The source/drain region formation is made dynamic through controlled epitaxial growth stages. The first portion is grown to a specific height, then selectively removed to create recesses at controlled depths, and finally regrown to a target height. This dynamic, multi-stage process enables precise control over the final cross-sectional area to reduce RC delay.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced gate-to-drain capacitance, faster on/off switching, and improved device speed by controlling the merge height and cross-sectional area of epitaxial source/drain regions.
Implementation Method 1
depositing a spacer material over fins and filling regions between adjacent fins
Implementation Method 2
depositing a spacer material over fins and filling regions between adjacent fins
Implementation Method 3
an etching process that ensures remaining spacer material between fins is higher than outside
Implementation Method 4
lateral epitaxial growth of source/drain regions, which merges at a higher distance above the substrate
Data Source
AI summary
A method includes forming a gate structure over fins protruding from a semiconductor substrate; forming an isolation region surrounding the fins; depositing a spacer layer over the gate structure and over the fins, wherein the spacer layer fills the regions extending between pairs of adjacent fins; performing a first etch on the spacer layer, wherein after performing the first etch, first remaining portions of the spacer layer that are within inner regions extending between pairs of adjacent fins have a first thickness and second remaining portions of the spacer layer that are not within the inner regions have a second thickness less than the first thickness; and forming an epitaxial source/drain region adjacent the gate structure and extending over the fins, wherein portions of the epitaxial source/drain region within the inner regions are separated from the first remaining portions of the spacer layer.