FUSI Gate Formation With Layered Polysilicon for HKMG MOSFETs
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Solution Overview
Problem
The challenge in forming MOSFET devices with fully silicided (FUSI) gates is the difficulty in embedding low voltage and high voltage devices together using high κ metal gate (HKMG) replacement gate processes, due to processing issues such as hump defects and non-uniform polysilicon layers, which can lead to incomplete silicidation and degraded performance.
Innovation Solution
A method is developed to form a MOSFET device with a gate structure comprising a high κ dielectric layer, a metal layer, and a thin, uniform polysilicon layer over the metal layer, followed by an annealing process to convert the polysilicon and conductive layer into a fully silicided layer, ensuring complete silicidation and minimizing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick polysilicon layer is used in FUSI gate formation, then the gate electrode can be fully silicided, but hump defects and non-uniformity occur leading to incomplete silicidation
Solution Approach 1:
The gate electrode is segmented into multiple layers: a thin uniform polysilicon layer (first thickness) and a thicker polysilicon layer (second thickness). The thin layer ensures uniformity and prevents hump defects, while the thicker layer provides sufficient material for complete silicidation. This segmentation resolves the contradiction by dividing the gate electrode into functional zones.
Solution Approach 2:
Different regions of the gate electrode are given different thicknesses to serve different functions. The first polysilicon layer has uniform thin thickness optimized for preventing hump defects, while the second polysilicon layer has greater thickness optimized for complete silicidation. This local differentiation allows each layer to optimize its specific function without compromising the other.
2Adaptability or versatility
If HKMG replacement gate process is used, then scaling can be achieved, but embedding low voltage and high voltage devices together becomes difficult due to processing issues
Solution Approach 1:
The gate electrode is divided into multiple polysilicon layers with different thicknesses, allowing independent optimization for different device types. This segmentation enables the same fabrication process to produce both low voltage and high voltage devices with appropriate gate characteristics, resolving the adaptability issue while maintaining manufacturing precision.
Solution Approach 2:
The multi-layer polysilicon gate structure serves multiple functions: it prevents hump defects, enables complete silicidation, and accommodates both low voltage and high voltage device requirements. This universal structure replaces the need for separate processing approaches for different device types, achieving versatility without sacrificing precision.
3Reliability
If polysilicon layer thickness is increased to ensure complete silicidation, then FUSI gate functionality is achieved, but hump defects occur degrading performance
Solution Approach 1:
The gate electrode is segmented into a thin first polysilicon layer that prevents hump defects and a thicker second polysilicon layer that ensures complete silicidation. By separating these conflicting requirements into distinct layers, the invention achieves FUSI gate functionality without generating hump defects.
Solution Approach 2:
The thin first polysilicon layer acts as an intermediary between the substrate and the thicker second polysilicon layer. This intermediate layer provides a uniform foundation that prevents hump defect formation while allowing the thicker layer to achieve complete silicidation, thus mediating between the conflicting requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the successful embedding of low voltage and high voltage devices on the same platform with minimal defects, ensuring complete silicidation and improved performance by maintaining a thin and uniform FUSI layer thickness, thus overcoming processing issues related to polysilicon layer thickness and hump defects.
Implementation Method 1
converting the polysilicon layer and conductive layer into a fully silicided (FUSI) layer
Implementation Method 2
converting the polysilicon layer and conductive layer into a fully silicided (FUSI) layer
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure over a substrate. A metal layer overlies the gate dielectric structure. A conductive layer overlies the metal layer. A polysilicon layer contacts opposing sides of the conductive layer. A bottom surface of the polysilicon layer is aligned with a bottom surface of the conductive layer. A dielectric layer overlies the polysilicon layer. The dielectric layer continuously extends from sidewalls of the polysilicon layer to an upper surface of the conductive layer.