Common Strain-Relaxed Buffer for Dual Channel FinFET
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Solution Overview
Problem
Current FinFET CMOS technologies face challenges in simultaneously enhancing mobility for both PMOS and NMOS transistors due to differing strain requirements, leading to performance degradation and increased complexity and cost in manufacturing.
Innovation Solution
A method involving a common strain-relaxed buffer layer and channel material for both nFinFET and pFinFET, with specific Ge concentrations and source/drain region designs to optimize strain and mobility, allowing for a reduced number of processing steps and materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple epitaxial growth steps of different types of strained-relaxed buffers and channels are performed, then mobility enhancement for both NMOS and PMOS transistors is achieved, but manufacturing complexity and cost increase due to required masking steps
Solution Approach 1:
The patent merges the buffer layer and channel layer into a single integrated structure where the strained-relaxed buffer layer serves both NMOS and PMOS transistors simultaneously. This eliminates the need for separate epitaxial growth steps and masking operations for each transistor type, reducing manufacturing complexity while maintaining mobility enhancement benefits.
Solution Approach 2:
The strained-relaxed buffer layer is designed to provide universal strain engineering benefits for both NMOS and PMOS transistors. By configuring the buffer layer with appropriate composition gradients and strain characteristics, it simultaneously enhances electron mobility in NMOS channels and hole mobility in PMOS channels, making a single structure serve multiple functions.
2Reliability
If strain engineering is applied to enhance mobility in one transistor type, then performance improves for that transistor, but performance degrades for the other transistor type due to opposite strain requirements
Solution Approach 1:
The patent applies local quality by creating spatially varying strain characteristics within the buffer layer. The buffer layer composition is tailored to provide tensile strain in regions affecting NMOS transistors and compressive strain in regions affecting PMOS transistors. This localized strain engineering allows each transistor type to receive its optimal strain type while sharing a common buffer structure.
Solution Approach 2:
The buffer layer is designed as a composite structure with varying semiconductor material compositions (e.g., SiGe with different Ge concentrations). This composite approach enables the buffer to exhibit different strain properties in different regions or orientations, simultaneously satisfying the opposite strain requirements of NMOS and PMOS transistors through material composition engineering.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved mobility and reduced manufacturing costs, with enhanced performance for both PMOS and NMOS FinFET devices, compatible with sub-10nm technology nodes, and simplifies high-volume production.
Implementation Method 1
Strain engineering refers to a general strategy employed in semiconductor manufacturing to enhance device performance. Performance benefits are achieved by modulating mechanical strain in the transistor channel, which enhances electron mobility (or hole mobility) and thereby conductivity through the channel.
Data Source
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AI summary
A CMOS semiconductor FinFET device and a method for manufacturing a CMOS semiconductor FinFET device is disclosed. The device comprises a NFinFET and PFinFET having a channel region comprising Ge on a common strain-relaxed buffer layer comprising SiGe. The concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer. The device further comprises a source/drain region for the NFINFET, the source/drain region comprising SiGe; and a source/drain region for the PFINFET, the second source/drain region comprising Ge.