FEOL FinFET MOS Capacitor Structure for Higher Capacitance Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of metal-insulator-metal (MIM) capacitors in the back-end-of-line (BEOL) of semiconductor chips introduces RC delays and restricts design flexibility, particularly in three-dimensional stacking applications, leading to image distortion in CMOS image sensor chips due to their location and bonding interface effects.
Innovation Solution
A FinFET MOS capacitor is integrated in the front-end-of-line (FEOL) with FinFET transistor devices, featuring a capacitor fin structure with heavily doped dummy source/drain regions and a dummy channel region, which enhances capacitance linearity and allows for greater capacitance without increasing the lateral footprint, using a capacitor gate structure separated by a thin gate dielectric.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MIM capacitors are integrated in the back-end-of-line (BEOL), then capacitance is provided, but RC delays increase and design flexibility is restricted
Solution Approach 1:
The patent transitions from planar BEOL capacitor integration to vertical FEOL FinFET MOS capacitor structure. By stacking the capacitor vertically using the fin structure's height dimension, capacitance is increased without lateral expansion, and RC delays are reduced by placing the capacitor closer to active devices in the vertical stacking architecture.
Solution Approach 2:
The patent merges the capacitor structure with the FinFET transistor fabrication process in the FEOL. The capacitor fin structure shares the same substrate and fabrication steps as adjacent transistors, integrating storage functionality directly into the logic layer rather than separating it into the BEOL interconnect layer.
2Quantity of substance
If capacitor size is increased to achieve higher capacitance, then capacitance increases, but lateral footprint increases
Solution Approach 1:
The patent exploits the vertical dimension by creating a FinFET MOS capacitor structure that extends upward from the substrate. The fin structure provides significant sidewall surface area for capacitance storage without increasing the lateral footprint, effectively moving capacitance generation from the planar domain to the vertical domain.
Solution Approach 2:
The heavily doped dummy channel region in the fin structure provides high capacitance density. The doping creates a region with enhanced electrical properties that increases capacitance per unit area, allowing higher capacitance values within the same lateral footprint.
3Quantity of substance
If FinFET MOS capacitor is integrated in FEOL with heavily doped dummy channel region and thin gate dielectric, then capacitance and linearity are enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent combines capacitor fabrication with transistor fabrication by using shared FEOL process steps. Both structures utilize the same fin formation, doping, and gate dielectric deposition processes, eliminating the need for separate capacitor manufacturing lines and reducing overall manufacturing complexity despite the enhanced capacitor features.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces RC delays and enhances design flexibility, improving the performance and integration of semiconductor chips by achieving greater capacitance and linearity, thus minimizing image distortion in stacked CMOS image sensor chips.
Implementation Method 1
FinFET MOS capacitor comprising a capacitor fin structure extending upwardly from an upper surface of a substrate. The capacitor fin structure comprises a pair of dummy source/drain regions separated by a dummy channel region
Implementation Method 2
a capacitor gate structure straddling on the capacitor fin structure, wherein the capacitor gate structure is separated from the capacitor fin structure by a thin capacitor gate dielectric
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a FinFET MOS capacitor. In some embodiments, the FinFET MOS capacitor comprises a substrate and a capacitor fin structure extending upwardly from an upper surface of the substrate. The capacitor fin structure comprises a pair of dummy source/drain regions separated by a dummy channel region and a capacitor gate structure straddling on the capacitor fin structure. The capacitor gate structure is separated from the capacitor fin structure by a capacitor gate dielectric.