Monolithic 3D IC Junctionless Devices via Layer Transfer
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Solution Overview
Problem
The manufacturing of monolithic 3D ICs faces challenges due to high-temperature annealing processes that can damage underlying layers, such as increasing metal resistance and causing metal contamination or compromising the integrity of silicide layers, while reducing annealing temperature reduces throughput and increases costs.
Innovation Solution
The method involves forming a first ILD layer over a semiconductor substrate with alternatingly stacked first vias and interconnect wires, transferring and patterning first and second doping-type semiconductor layers with opposite doping types to form junctionless semiconductor devices (JSDs) without performing ion implantation or annealing, thereby avoiding exposure to high temperatures that could damage underlying layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature annealing processes are used to form semiconductor devices, then device performance is improved, but underlying layers are damaged including increased metal resistance and metal contamination
Solution Approach 1:
The patent divides the semiconductor manufacturing process into separate stages: forming the first semiconductor layer with high-temperature annealing on a first substrate, then transferring it to a second substrate. This segmentation isolates the high-temperature process from the underlying sensitive layers, resolving the contradiction between achieving device performance and preventing damage to underlying structures.
Solution Approach 2:
The patent uses a first substrate as an intermediary carrier during the high-temperature annealing process. This intermediary substrate protects the final device structure from thermal damage while enabling the necessary high-temperature processing. The first substrate acts as a temporary platform that can withstand high temperatures without damaging the underlying layers that will eventually be formed.
2Object-affected harmful factors
If annealing temperature is reduced to protect underlying layers, then damage to underlying layers is minimized, but manufacturing throughput decreases and costs increase
Solution Approach 1:
By segmenting the manufacturing process into separate substrate stages, the patent enables high-temperature annealing to be performed efficiently on the first substrate without compromising underlying layers. This maintains manufacturing throughput and cost-effectiveness while protecting the final device structure, as the high-temperature step is isolated to a dedicated processing stage.
Solution Approach 2:
The patent performs the high-temperature annealing process in advance on the first substrate before transferring the semiconductor layer to the final substrate. This preliminary action allows aggressive thermal processing to be completed early in the manufacturing flow when it is most efficient, avoiding the need for temperature compromises that would reduce throughput.
3Power
If multiple semiconductor layers are stacked to form 3D ICs, then processing capabilities and power consumption are improved, but process limitations make it difficult to continue shrinking minimum feature size
Solution Approach 1:
The patent transitions from two-dimensional planar device scaling to three-dimensional stacked device architecture. By forming multiple semiconductor layers vertically stacked on different substrates and connecting them through through-silicon vias, the invention achieves continued performance improvement without further shrinking the minimum feature size in the lateral dimension, thereby overcoming the stated contradiction.
Data Source
AI summary
A method for manufacturing a monolithic three-dimensional (3D) integrated circuit (IC) with junctionless semiconductor devices (JSDs) is provided. A first interlayer dielectric (ILD) layer is formed over a semiconductor substrate, while also forming first vias and first interconnect wires alternatingly stacked in the first ILD layer. A first doping-type layer and a second doping-type layer are transferred to a top surface of the first ILD layer. The first and second doping-type layers are stacked and are semiconductor materials with opposite doping types. The first and second doping-type layers are patterned to form a first doping-type wire and a second doping-type wire overlying the first doping-type wire. A gate electrode is formed straddling the first and second doping-type wires. The gate electrode and the first and second doping-type wires at least partially define a JSD.