Grid-Like Stacked Capacitor for Semiconductor Miniaturization
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Solution Overview
Problem
Current semiconductor devices with nonvolatile memory require large capacitive elements for power supply circuits, occupying significant space and increasing the planar dimensions, which hinders further miniaturization and cost reduction.
Innovation Solution
A semiconductor device with a stacking-type capacitive element is developed, featuring a grid-like lower electrode and parallel-coupled capacitors, allowing for increased capacitance without adding extra manufacturing steps, thereby reducing the area occupied by the capacitive element while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single-layer capacitive element is used, then the manufacturing process is simple, but the capacitance per unit area is insufficient
Solution Approach 1:
The patent transitions from a single-layer capacitive structure to a multi-layer stacking configuration. By adding vertical dimensionality with multiple capacitor layers stacked on top of each other, the total capacitance increases without proportionally increasing the planar area occupation, thus resolving the contradiction between achieving high capacitance and minimizing device area.
Solution Approach 2:
The patent implements nested capacitor structures where multiple capacitive elements are stacked vertically with shared electrodes. The lower electrode of one capacitor serves as the upper electrode of the capacitor below it, creating a nested configuration that maximizes capacitance density within the available vertical space while reducing the overall footprint area.
2Area of stationary object
If the capacitive element area is reduced, then the microcomputer size is reduced, but the capacitance value decreases
Solution Approach 1:
By utilizing the vertical dimension through multi-layer stacking, the patent achieves high capacitance values within a compact planar footprint. The stacked configuration allows capacitance to scale with the number of layers rather than requiring proportional increases in horizontal area, enabling miniaturization while maintaining required capacitance.
Solution Approach 2:
The patent employs composite dielectric structures with multiple insulating layers having different material properties. This composite approach optimizes the capacitance-to-area ratio by selecting materials with appropriate dielectric constants and thicknesses, allowing high capacitance density within reduced device dimensions.
3Quantity of substance
If multiple capacitive layers are stacked, then the capacitance increases, but the manufacturing complexity increases
Solution Approach 1:
The patent merges multiple capacitor structures into a unified stacked configuration where adjacent capacitors share common electrodes. This merging approach increases total capacitance while reducing the number of discrete electrode structures that would need to be independently fabricated, thereby limiting the increase in manufacturing complexity despite the multi-layer architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a capacitive area at least twice that of single-layer capacitive elements with the same planar dimensions, reducing the area of the power supply circuit and lowering the overall cost of microcomputers with nonvolatile memory.
Implementation Method 1
a capacitive element large in occupied area, for generating a high voltage for write/erase operations
Data Source
AI summary
In a semiconductor device comprising a capacitive element, an area of the capacitive element is reduced without impairing performance, and further, without addition of an extra step in a manufacturing process. A first capacitor is formed between an active region of a semiconductor substrate provided through a first capacitive insulating film and a lower electrode comprised of a conductor film in the same layer as a select gate electrode of a select, a second capacitor is formed between the lower electrode, and an upper electrode comprised of a conductor film in the same layer as a memory gate electrode of a memory, provided through the second capacitive insulating film in the same layer as the insulating films of a multi-layer structure, including a charge storage layer, and a stacking-type capacitive element is comprised of the first capacitor and the second capacitor, wherein a planar shape of the lower electrode is a grid-like shape having a plurality of lengths of linear conductor films each having a first width, formed along a first direction with a first interval provided therebetween, and a plurality of lengths of linear conductor films each having a second width, formed along a second direction (the direction intersecting the first direction) with a second interval provided therebetween.