Core-Shell Nanostructured Channels for Higher-Mobility GAA FETs
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing charge carrier mobility in FET devices, which limits their switching speeds and drive currents due to the complexity of scaling down semiconductor devices.
Innovation Solution
The implementation of core-shell nanostructures, where nanostructured core regions are wrapped by epitaxially grown nanostructured shell regions, induces strain and tunes the energy bandgap and crystal orientation in channel regions, enhancing charge carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to increase storage capacity and processing speed, then device density and integration are improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements core-shell nanostructures where nanoscale core regions are nested within shell regions, creating a hierarchical structure that enables precise control of channel properties. This nested architecture allows multiple functional layers to be integrated at the nanoscale, achieving high device density and performance without proportionally increasing manufacturing complexity through self-aligned growth processes.
Solution Approach 2:
The patent employs systematic parameter changes in the core-shell structure, including varying shell thickness (5-50 nm), core material composition (Si, Ge, SiGe), and crystal orientation to optimize charge carrier mobility. By tuning these parameters, the invention achieves enhanced device performance while maintaining compatibility with existing semiconductor manufacturing processes.
2Ease of manufacture
If conventional FET structures are used, then manufacturing is simpler, but charge carrier mobility and switching speed are limited
Solution Approach 1:
The patent utilizes composite core-shell structures combining different semiconductor materials (e.g., Si core with Ge shell, or SiGe core with Si shell) to achieve properties not possible with single materials. The composite structure enables simultaneous optimization of lattice matching, strain engineering, and bandgap control, thereby enhancing charge carrier mobility and switching speed while maintaining manufacturability through established epitaxial growth techniques.
Solution Approach 2:
The patent applies local quality enhancement by introducing strain through the core-shell interface specifically in the channel region where it is most needed. The shell material is engineered to induce compressive or tensile strain locally in the channel, improving carrier mobility precisely where required without affecting other device regions, thus achieving performance enhancement with minimal impact on overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases switching speeds and drive currents of FET devices by 20% to 50% compared to devices without core-shell nanostructures, improving overall performance.
Implementation Method 1
induces strain and tunes the energy bandgap and crystal orientation in channel regions, enhancing charge carrier mobility
Implementation Method 2
nanostructured core regions are wrapped by epitaxially grown nanostructured shell regions
Data Source
AI summary
The structure of a semiconductor device with core-shell nanostructured channel regions between source/drain regions of FET devices and a method of fabricating the semiconductor device are disclosed. A semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate, and nanostructured shell regions wrapped around the second nanostructured regions. The nanostructured shell regions and the second nanostructured regions have semiconductor materials different from each other. The semiconductor device further includes first and second source/drain (S/D) regions disposed on the substrate and a gate-all-around (GAA) structure disposed between the first and second S/D regions, Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions and the GAA structure is wrapped around each of the nanostructured shell regions.