Array Substrate Gate Line Deformation Prevention
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Solution Overview
Problem
The degradation of thin film transistors in array substrates due to the difference in thickness of the semiconductor layer and the deformation of signal lines made from low resistance metals at high temperatures, leading to signal delay and increased defect rates in large-sized display devices.
Innovation Solution
A method of fabricating an array substrate using a high melting point metal layer, followed by heat-treating an oxide semiconductor layer, and then patterning the metal and semiconductor layers to form a gate electrode and gate line, which reduces deformation and misalignment, and using a double-layered structure for source and drain electrodes to improve carrier mobility and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low resistance metal material is used for gate line to reduce signal delay, then signal transmission performance is improved, but deformation and misalignment occur at high temperatures
Solution Approach 1:
The gate electrode structure is divided into two separate components: a gate electrode formed from high melting point metal (Mo, Ti, or W) that maintains structural integrity at high temperatures, and a gate line formed from low resistance metal material (Al, Al alloy, or Cu) that provides excellent signal transmission. This segmentation allows each component to be optimized for its specific function without the trade-offs that would exist in a single-material structure.
Solution Approach 2:
The gate electrode is formed first through deposition and patterning processes, establishing a stable high-temperature structure. Subsequently, the gate line is formed in a later process step using low resistance metal material. This preliminary action of creating the temperature-stable structure before adding the low resistance layer ensures that the gate line can be deposited without causing deformation, while still achieving low signal delay.
2Reliability
If oxide semiconductor layer is heat-treated at high temperature to improve mobility, then carrier mobility is enhanced, but metal layers deform and misalign
Solution Approach 1:
The material composition of the gate electrode is changed from low melting point metals to high melting point metals (Mo, Ti, or W), fundamentally altering the thermal stability parameter. This parameter change enables the gate electrode to withstand the high temperature heat treatment (300-500°C) required for oxide semiconductor layer activation without deforming, thereby maintaining alignment precision while achieving the necessary carrier mobility enhancement.
3Device complexity
If single-layered oxide semiconductor layer is used to simplify structure, then fabrication complexity is reduced, but thickness variation degrades transistor performance
Solution Approach 1:
The oxide semiconductor layer is formed with spatially varying thickness to achieve different functional qualities in different regions. The layer has a first thickness in the switching region where transistor performance is critical, and a second thickness in the gate electrode region where electrical connection is prioritized. This local quality variation optimizes both transistor reliability and electrical performance without requiring a completely different single-layer structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents deformation and misalignment of the gate line, enhances the reliability and mobility of the oxide semiconductor layer, reduces signal delay, and simplifies the fabrication process, thereby improving the production rate and reducing costs.
Implementation Method 1
heat-treating the substrate having the oxide semiconductor material layer at a temperature of about 300 degrees Celsius to about 500 degrees Celsius
Data Source
AI summary
A method of fabricating an array substrate includes forming a first metal layer, a gate insulating material layer and an oxide semiconductor material layer on a substrate; heat-treating the substrate having the oxide semiconductor material layer at a temperature of about 300 degrees Celsius to about 500 degrees Celsius; patterning the oxide semiconductor material layer, the gate insulating material layer and the first metal layer, thereby forming a gate electrode, a gate insulating layer and an oxide semiconductor layer; forming a gate line connected to the gate electrode and made of low resistance metal material; forming source and drain electrodes, a data line and a pixel electrode, the source and drain electrodes and the data line having a double-layered structure of a transparent conductive material layer and a low resistance metal material layer, the pixel electrode made of the transparent conductive material layer.