Parasitic PIN Device in BiCMOS Process for Low Insertion Loss
Solution Overview
Problem
Conventional BiCMOS processes face challenges in fabricating parasitic PIN devices with low insertion loss and high isolation without introducing additional process conditions, which affects the efficiency and cost-effectiveness of semiconductor integrated circuits.
Innovation Solution
A parasitic PIN device is formed on a P-type silicon substrate using shallow trench isolation oxide layers, with N-type pseudo buried layers, N-type collector implantation regions, and a P-type intrinsic base epitaxial layer, implemented through existing BiCMOS process conditions, including ion implantation and thermal annealing, to achieve low insertion loss and high isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional BiCMOS process uses heavily doped collector region buried layers to reduce collector region resistance, then collector region resistance is reduced, but the process complexity increases and additional process conditions are required
Solution Approach 1:
The patent utilizes existing BiCMOS process steps (N-type collector implantation, P-type base implantation, epitaxial growth) to automatically form the PIN device structure without requiring separate dedicated process steps. The parasitic PIN device is created as a byproduct of the normal bipolar transistor fabrication process, making the process self-serving and eliminating additional complexity.
Solution Approach 2:
The existing BiCMOS process steps serve multiple functions: they create both the bipolar transistor structure and the parasitic PIN device structure simultaneously. The N-type collector implantation and P-type base implantation serve dual purposes of forming the transistor while also creating the PIN diode structure, achieving multi-functionality without additional process conditions.
2Reliability
If additional process conditions are introduced to fabricate parasitic PIN device, then device performance is improved, but manufacturing cost increases
Solution Approach 1:
The fabrication process uses the existing BiCMOS process steps to automatically create the PIN device structure without requiring additional dedicated process steps. The same ion implantation and epitaxial growth steps that form the bipolar transistor also form the PIN device, making the process self-serving and eliminating additional manufacturing costs.
Solution Approach 2:
The patent merges the formation of the bipolar transistor structure and the PIN device structure into a single integrated process flow. The N-type collector implantation, P-type base implantation, and epitaxial growth steps simultaneously create both device types, combining multiple functions into unified process steps and reducing overall manufacturing cost.
3Loss of energy
If N-type pseudo buried layers are formed by ion implantation with specific parameters, then N-type region conductivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent specifies optimized parameter ranges for ion implantation (dose: 1e14-1e16 cm^-2, energy: <30 KeV) that balance conductivity improvement with manufacturing feasibility. By defining appropriate parameter windows rather than single-point specifications, the process achieves good conductivity while maintaining tolerance for normal manufacturing variations.
Solution Approach 2:
The N-type pseudo buried layers are formed with specific local properties (impurity concentration: 1e19-1e21 cm^-3) at the bottom of shallow trench isolation oxide layers, creating locally optimized conductivity without requiring high precision across the entire wafer. The localized nature of the implantation allows for relaxed precision requirements while achieving the desired conductivity improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in a parasitic PIN device with low insertion loss of less than 2 dB and high isolation of more than 30 dB, suitable for microwave and radio frequency applications, while maintaining existing process conditions and reducing manufacturing costs.
Implementation Method 1
The N-type pseudo buried layers are formed by ion implantation at the bottom of the shallow trench isolation oxide layers
Implementation Method 2
conduct thermal annealing to the silicon substrate. The N-type region will extend vertically and laterally into the active region and contact with the I-type region during the thermal annealing process
Implementation Method 3
form an intrinsic base epitaxial layer on the surface of the active region, and form a P-type region by P-type extrinsic base region ion implantation into the intrinsic base epitaxial layer
Implementation Method 4
The intrinsic base epitaxial layer of the P-type region is a P-doped silicon epitaxial layer or a P-doped Silicon-Germanium epitaxial layer, or a P-doped Carbon-Silicon-Germanium epitaxial layer, which is formed by in-situ P-doping
Data Source
AI summary
A parasitic PIN device in a BiCMOS process is disclosed. The device is formed on a silicon substrate, in which an active region is isolated by shallow trenches. The device includes: an N-type region, consisting of N-type pseudo buried layers respectively formed at the bottom of shallow trench isolation oxide layers and extending into the active region; an I-type region, consisting of an N-type collector implantation region formed in the active region and contacting with the N-type region; a P-type region, consisting of a P-doped intrinsic base epitaxial layer on a surface of the active region and contacting with the I-type region. The device of the present invention has a low insertion loss and a high isolation. A manufacturing method of parasitic PIN device in compatible with existing BiCMOS process is also disclosed.