Charge-Trapping Layer Optimization for Fast NOR Memory Programming
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Solution Overview
Problem
Conventional NOR-type and NAND-type memory devices face challenges in maintaining endurance due to the trade-off between fast program and erase times and the magnitude of voltages used, leading to degradation in charge-trapping layers and non-uniform threshold voltages across memory cells, necessitating iterative read-verify procedures to ensure accurate programming and erasing.
Innovation Solution
An optimized charge-trapping layer with a reduced number of charge-trapping sites and lower electric field across the tunnel oxide layer, utilizing silicon-rich nitride or nano-crystals like germanium, zirconium oxide, or zinc oxide, allows for efficient programming and erasing with reduced programming and erase times, eliminating the need for read-verify procedures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high voltage is applied to achieve fast program and erase times, then programming and erasing speed is improved, but charge-trapping layer degradation increases and endurance worsens
Solution Approach 1:
The patent changes the physical and chemical parameters of the charge-trapping layer by using silicon-rich nitride with specific refractive index (2.05 or greater) and controlled trap site density. This material parameter change enables fast programming/erasing at reduced voltages (15.0V or less), resolving the contradiction between speed and reliability by allowing high-speed operation without the damaging high voltages that cause degradation
Solution Approach 2:
The patent employs a composite structure consisting of multiple oxide layers (tunnel oxide, blocking oxide) combined with a silicon-rich nitride charge-trapping layer containing nano-crystals of germanium, zirconium oxide, or zinc oxide. This composite material design creates a charge-trapping layer with optimized electrical properties that achieves fast switching speeds while maintaining durability and reducing voltage-induced degradation
2Speed
If high voltage is applied to achieve fast program and erase times, then programming and erasing speed is improved, but threshold voltage uniformity deteriorates
Solution Approach 1:
By changing the material composition to silicon-rich nitride with controlled refractive index and trap site density, the patent achieves uniform charge trapping characteristics across all memory cells. This parameter optimization allows threshold voltages to be uniformly shifted during programming and erasing operations, maintaining precision even with reduced pulse widths of 500 nanoseconds or less
Solution Approach 2:
The patent creates localized charge-trapping sites within the charge-trapping layer that can be precisely controlled in density and distribution. This local quality control ensures uniform electrical characteristics across the memory device, enabling consistent threshold voltage shifts without the non-uniformity that typically plagues high-speed operations
3Ease of manufacture
If conventional charge-trapping layers are used, then manufacturing is simpler, but read-verify procedures are required increasing device complexity
Solution Approach 1:
The patent optimizes the charge-trapping layer parameters (silicon-rich nitride composition, refractive index of 2.05 or greater, controlled trap site density) to achieve reliable single-pulse programming and erasing. This parameter optimization eliminates the need for iterative read-verify procedures, reducing control circuit complexity while maintaining manufacturability through standard semiconductor fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The optimized charge-trapping layer enhances endurance by maintaining threshold voltage consistency across memory cells, reducing programming and erase times, and achieving narrower distributions of threshold voltages in programmed and erased states.
Implementation Method 1
an applied electrical field across a charge-trapping layer adds or removes charge from traps in the charge-trapping layer
Implementation Method 2
By placing a high voltage of the opposite polarity on gate conductor 70, electrons are withdrawn from charge-trapping layer 70
Data Source
AI summary
A thin-film memory transistor includes a source region, a drain region, a channel region, a gate electrode, and a charge-trapping layer provided between the channel region and the gate electrode and electrically isolated therefrom, wherein the charge-trapping layer has includes a number of charge-trapping sites that is 70% occupied or evacuated using a single voltage pulse of a predetermined width of 500 nanoseconds or less and a magnitude of 15.0 volts or less. The charge-trapping layer comprises silicon-rich nitride may have a refractive index of 2.05 or greater or comprises nano-crystals of germanium (Ge), zirconium oxide (ZrO2), or zinc oxide (ZnO). The thin-film memory transistor may be implemented, for example, in a 3-dimensional array of NOR memory strings formed above a planar surface of a semiconductor substrate.