Salicided Gate and Source Drain Fabrication for CMOS Image Sensors
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Solution Overview
Problem
Conventional integrated circuit manufacturing processes face limitations in reducing device feature size and achieving higher circuit density due to challenges in forming contact structures for MOS transistor devices, particularly with silicided metal layers, which are complex and restrictive.
Innovation Solution
A method for manufacturing silicided and non-silicided MOS transistor structures involves forming trench isolation, gate polysilicon layers, silicide layers, sidewall spacers, and blocking layers to create both silicided and non-silicided regions, allowing for higher device yields and compatibility with conventional technology without significant equipment modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicided metal layers are used to form contact structures for MOS transistor devices, then electrical conductivity is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies different treatments to different regions of the semiconductor device. Specifically, silicide is formed in the first device region to improve conductivity where needed, while the second device region remains non-silicided to simplify processing and reduce complexity. This local differentiation resolves the contradiction by providing high conductivity only where necessary rather than uniformly across the entire device.
2Productivity
If device feature size is reduced to increase circuit density, then circuit density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the semiconductor device into multiple distinct regions (first device region and second device region) with different characteristics. This segmentation allows each region to be optimized independently - the silicided region provides high conductivity for dense interconnections, while the non-silicided region maintains simpler processing requirements, thereby enabling higher overall circuit density without uniformly increasing precision demands across the entire device.
3Ease of manufacture
If conventional fabrication processes are used, then manufacturing cost is reduced, but adaptability to different device configurations is limited
Solution Approach 1:
The patent creates a universal fabrication approach that can accommodate multiple device configurations within a single process flow. By incorporating both silicided and non-silicided regions in the same device structure, the method becomes adaptable to different circuit design requirements while still using conventional fabrication techniques, thus achieving both cost-effectiveness and process flexibility.
Data Source
AI summary
A method for fabricating an integrated circuit device, e.g., CMOS image sensor. The method includes providing a semiconductor substrate, which has a first device region and a second device region. The method forms a gate polysilicon layer overlying the first and second device regions. The method forms a silicide layer overlying the gate polysilicon layer. The method patterns the silicide layer and gate polysilicon layer to form a first silicided gate structure in the first device region and a second silicided gate structure in the second device region. The method also includes forming a blocking layer overlying the second device region. The method forms a silicide material overlying a first source region and a first drain region associated with the first silicided gate structure, and maintaining a second source region and a second drain region associated with the second silicided gate structure free from any silicide using the blocking layer.