DeMOS Transistor Retrograde Well ESD Immunity
Solution Overview
Problem
Conventional drain extended field effect transistors (DeMOS) are susceptible to electrostatic discharge (ESD) damage, requiring additional protective circuitry that increases chip cost and compromises performance due to poor ESD immunity and thermal failure mechanisms.
Innovation Solution
The design incorporates a retrograde well with a shallower layer and a deeper layer of higher doping, coupled with an extended drain region and isolation region, to distribute charge carriers and reduce localized current concentration, thereby enhancing ESD immunity without compromising normal FET operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DeMOS transistor structure is used, then device can operate with simple construction, but device suffers from poor ESD immunity and requires additional protective circuitry
Solution Approach 1:
The drain region is segmented into multiple zones with different doping concentrations (first doping concentration in the extended drain region, second doping concentration in the main drain region). This segmentation allows the extended drain region to handle ESD stress while the main drain region maintains normal operation, thereby improving ESD immunity without requiring additional protective circuitry.
Solution Approach 2:
The patent applies local quality by creating a retrograde well with varying doping concentrations at different locations and depths. The extended drain region has a first doping concentration optimized for ESD protection, while the main drain region has a second doping concentration optimized for normal operation. This localized optimization resolves the contradiction between ESD immunity and device simplicity.
2Reliability
If additional ESD protection circuitry is added to DeMOS transistor, then ESD immunity is improved, but chip cost increases
Solution Approach 1:
The retrograde well structure serves multiple functions: it enables normal FET operation while simultaneously providing ESD protection. The extended drain region with first doping concentration handles both regular current flow and ESD stress, eliminating the need for separate ESD protection circuitry and reducing chip cost.
Solution Approach 2:
The patent merges the ESD protection function into the normal transistor structure by creating a retrograde well where the extended drain region serves dual purposes. This combination of functions within a single structure avoids the need for additional protective circuitry, thereby reducing manufacturing complexity and chip cost while maintaining ESD immunity.
3Reliability
If drain extended region is created in retrograde well, then charge carriers are distributed and ESD immunity is enhanced, but device complexity increases
Solution Approach 1:
The patent changes the doping concentration parameter within the retrograde well to create the extended drain region. By varying the doping concentration from the first value in the extended drain region to the second value in the main drain region, the structure achieves improved charge carrier distribution and ESD immunity while maintaining a relatively simple overall device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly improves ESD immunity, allowing DeMOS transistors to withstand higher ESD stress without additional protection circuitry, ensuring reliable operation and reduced chip costs.
Implementation Method 1
distribute charge carriers and reduce localized current concentration
Implementation Method 2
electrostatic discharge (ESD) is the transfer of an electrostatic charge between bodies at different electrostatic potentials
Data Source
AI summary
In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.