SOI Bipolar Transistor Resurf Biasing for Breakdown Voltage
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Solution Overview
Problem
Conventional SOI bipolar transistors face a tradeoff between high frequency performance and high bias voltage, requiring separate manufacturing for high voltage and high performance devices, which increases costs and manufacturing complexity.
Innovation Solution
The integration of both NPN and PNP high voltage transistors on the same substrate using an SOI semiconductor structure with a buried insulator layer, where donor impurities are implanted under the p-type region for PNP transistors and acceptor impurities under the n-type region for NPN transistors, allowing for increased breakdown voltage without altering collector doping or thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the collector region is lightly doped and made thicker to increase breakdown voltage, then high voltage performance is improved, but high frequency performance deteriorates due to increased parasitic capacitance and reduced switching speed
Solution Approach 1:
The collector region is divided into two distinct parts: a lightly doped and thicker portion extending to the substrate for high voltage breakdown, and a heavily doped region near the collector-base junction for high frequency performance. This segmentation allows each region to independently optimize its function without compromising the other.
Solution Approach 2:
Different doping concentrations and thicknesses are applied to different spatial locations within the collector region. The region near the collector-base junction has heavy doping for low parasitic capacitance and fast switching, while the region extending to the substrate has light doping and greater thickness for high breakdown voltage.
2Reliability
If separate manufacturing processes are used for high voltage and high performance integrated circuits, then device performance is optimized, but manufacturing complexity and cost increase
Solution Approach 1:
Both high voltage and high frequency performance characteristics are integrated into a single bipolar transistor device structure using one unified manufacturing process. The dual-region collector design enables the same fabrication process to produce transistors that simultaneously achieve high breakdown voltage and high frequency performance.
Solution Approach 2:
The bipolar transistor structure is designed to perform multiple functions: it achieves high voltage breakdown capability through the lightly doped collector region while simultaneously maintaining high frequency performance through the heavily doped region near the junction, all within a single device and manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the breakdown voltage of PNP transistors while maintaining high voltage performance for NPN transistors, eliminating the need for separate manufacturing and reducing manufacturing costs and complexity.
Implementation Method 1
The buried oxide layer isolates the active devices from the underlying substrate, effectively eliminating parasitic nonlinear junction capacitances to the substrate
Implementation Method 2
an n-type region is included under the buried insulator layer BOX of the PNP transistor, by implanting donor impurities of through the active device region of the SOI wafer and BOX into the p-type region
Implementation Method 3
What is needed is a method of increasing PNP BV without decreasing collector doping concentration or increasing collector region thickness of the PNP while including a high voltage NPN on the same circuit/substrate
Data Source
AI summary
Complementary high-voltage bipolar transistors in silicon-on-insulator (SC) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV.