Dual-Transistor Semiconductor Memory for Refresh-Free Data Storage
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in storing data long-term without power, with volatile memory devices requiring frequent refresh operations and non-volatile memory devices experiencing limitations in writing cycles and high voltage requirements.
Innovation Solution
A semiconductor device is developed using a highly purified oxide semiconductor with a layered structure of transistors, including one using a material other than oxide semiconductor and another using oxide semiconductor, which reduces leakage current and eliminates the need for high voltage writing, allowing for long-term data storage without refresh operations and unlimited writing cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a volatile memory device (DRAM) is used to store data, then writing and reading operations can be performed quickly, but data is lost when power supply stops and refresh operations are required at predetermined intervals
Solution Approach 1:
The patent divides the memory system into two distinct memory elements: a first memory element using a transistor with high mobility for fast writing/reading operations, and a second memory element using a transistor with low leakage current for long-term data retention. This segmentation allows each element to specialize in its respective function, resolving the contradiction between speed and reliability.
Solution Approach 2:
The patent combines two different transistor technologies into a single memory device structure. The first transistor (high mobility) and second transistor (low leakage) are integrated to work together, where the first handles fast operations and the second ensures data retention, thus merging the advantages of both approaches.
2Reliability
If flash memory is used for long-term storage, then refresh operations are not needed, but high voltage is necessary for holding or removing charge in the floating gate
Solution Approach 1:
The patent changes the operating voltage parameter by using a different charge storage mechanism. Instead of using high voltage to inject charge into a floating gate (as in flash memory), the invention uses low voltage to control charge in a capacitor, thereby achieving long-term retention without high voltage requirements.
3Reliability
If SRAM is used to store data, then refresh operations are not needed, but cost per storage capacity is increased
Solution Approach 1:
The patent applies local quality by using different transistor types in different locations within the memory cell. The first transistor uses high mobility material for fast switching, while the second transistor uses low leakage material for retention, allowing the device to achieve SRAM-like retention without the full complexity of SRAM circuits.
Data Source
AI summary
An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.