Hexagonal Lattice Memory Device with Vertical GAA Transistors
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing memory density and reducing manufacturing costs while maintaining high data retention and off-leakage characteristics, particularly in miniaturizing memory cells without compromising performance.
Innovation Solution
The proposed solution involves a memory device configuration with a hexagonal lattice arrangement of memory cells, utilizing vertical transistors with a gate-all-around (GAA) structure and oxide semiconductor layers, where bit lines are formed above the transistors in a zigzag pattern, and cell capacitors are placed below, allowing for self-aligned coupling without additional pad layers and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are miniaturized to increase memory density, then memory density is improved, but data retention and off-leakage characteristics deteriorate
Solution Approach 1:
The patent transitions from planar transistor structures to vertical transistors with gate-all-around (GAA) structure, moving the transistor channel from a 2D plane to a 3D vertical configuration. This dimensional change allows for better gate control over the channel while maintaining smaller footprint area, thus increasing memory density without compromising data retention characteristics.
Solution Approach 2:
The patent employs oxide semiconductor layers as the channel material in vertical transistors. Oxide semiconductors provide superior electrical characteristics including low off-leakage current and high carrier mobility, which directly address the reliability concerns associated with miniaturized memory cells while enabling higher density integration.
2Manufacturing precision
If additional pad layers are added for self-aligned coupling of bit lines and capacitors, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent implements self-aligned coupling by pre-positioning the bit lines and capacitors in specific spatial relationships during earlier manufacturing stages. The vertical transistor structure and hexagonal lattice arrangement are designed such that subsequent layers automatically align with previous layers without requiring additional alignment layers or complex alignment procedures, thus achieving high precision while limiting complexity increase.
Data Source
AI summary
According to one embodiment, a memory includes: a first transistor including: a first semiconductor between the substrate and the bit line; and a first gate facing a side of the first semiconductor; a first memory element between the first transistor and the substrate; a first word line including a first conductor coupled to the first gate; a second transistor including: a second semiconductor between the substrate and the bit line; and a second gate facing a side of the second semiconductor; a second memory element between the second transistor and the substrate; and a second word line being adjacent to the first word line in a first direction and including a second conductor coupled to the second gate. The second semiconductor is adjacent to the first semiconductor in a second direction intersecting the first direction.