OLED Pixel Connection Layout With Shared Openings for Higher Resolution

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Solution Overview

Problem

The challenge in implementing high-resolution OLED displays is the increase in pixel size due to the number of openings required to connect transistors, which affects the distance between electrodes and overall display resolution.

Innovation Solution

The design reduces the number of openings by directly connecting transistors using a second connection electrode that contacts the first connection electrode, allowing for a more compact pixel structure and improved resolution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the number of openings is increased to connect transistors, then the connection reliability is improved, but the pixel size increases and resolution decreases

Engineering Contradiction:
Improveconnection reliabilityVSAvoidpixel size
Core Design Contradiction:
ReliabilityVSArea of moving object

Solution Approach 1:

The patent merges multiple connection functions into a single opening structure. The first connection electrode connects the first transistor to the second transistor, while the second connection electrode connects the second transistor to the third transistor, both through the same opening in the insulation layer. This consolidation reduces the total number of openings required, thereby minimizing pixel size while maintaining reliable electrical connections between all transistors.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent utilizes vertical stacking in the third dimension by placing connection electrodes at different heights. The first connection electrode is positioned at a first height and the second connection electrode at a second height within the same opening, allowing multiple electrical connections to be achieved vertically rather than requiring separate horizontal openings. This dimensional approach reduces the planar footprint of each pixel.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of moving object

If the number of openings is reduced to minimize pixel size, then the resolution is improved, but the connection complexity increases

Engineering Contradiction:
Improvepixel sizeVSAvoidconnection complexity
Core Design Contradiction:
Area of moving objectVSDevice complexity

Solution Approach 1:

The patent segments the connection function into multiple electrodes positioned at different heights within the same opening. The first connection electrode handles the connection to the second transistor, while the second connection electrode handles the connection to the third transistor. This segmentation allows complex multi-transistor connections to be achieved through a single opening, reducing pixel size while managing connection complexity through structured electrode arrangement.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The second transistor serves as an intermediary element that connects the first and third transistors. By routing connections through this intermediate transistor using shared openings, the patent simplifies the overall connection architecture. The intermediary transistor enables signal and power transmission between non-adjacent transistors without requiring direct connections, thereby reducing the total number of openings needed.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11825703B2Display device and method for manufacturing thereof
Publication Date: 2023.11.21 SAMSUNG DISPLAY CO LTD
  • US11825703B2 patent drawing
  • US11825703B2 patent drawing
  • US11825703B2 patent drawing

AI summary

A display device includes a substrate, a first transistor including a channel on the substrate, a first electrode and a second electrode, and a gate electrode overlapping the channel of the first transistor, a first interlayer insulation layer on the first and second electrodes of the first transistor, a second transistor including a channel disposed on the first interlayer insulation layer, a first electrode and a second electrode of the second transistor, and a gate electrode that overlaps the channel of the second transistor, a first connection electrode disposed on the first interlayer insulation layer, and connected with the first electrode of the first transistor, a gate insulation layer disposed between the first interlayer insulation layer and the first connection electrode, and a second connection electrode that connects the first connection electrode and the first electrode of the second transistor.