Dual Structure FinFET Vertical Stacking Integration Density
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Solution Overview
Problem
Conventional FinFETs face limitations in integration density due to the formation of N-type and P-type transistors on the same plane, with P-type transistors requiring wider widths to match current drivability, leading to increased area and reduced integration density, and existing dual structure FinFET manufacturing methods are complex and difficult to implement.
Innovation Solution
A dual structure FinFET is developed with a solid source material layer between N-type and P-type FinFETs, using epitaxially grown silicon or silicon germanium for increased carrier mobility, and a buried oxide layer formed by SIMOX to vertically insulate NMOS and PMOS, allowing for raised source and drain formation without complex ion implantation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If N-type and P-type transistors are formed on the same plane, then the device can be manufactured using conventional processes, but the integration density is not significantly enhanced and the area increases
Solution Approach 1:
The patent transitions from planar (2D) transistor arrangement to vertical (3D) stacking, where N-type and P-type FinFETs are stacked one above the other. This dimensional change allows both transistor types to share the same footprint area while providing electrical isolation through the buried oxide layer, thereby increasing integration density without compromising manufacturability
Solution Approach 2:
The patent divides the transistor structure into separate N-type and P-type FinFET units that can be independently designed and manufactured. Each FinFET is a self-contained device with its own source, drain, and gate, allowing modular stacking and simplifying the manufacturing process while reducing overall area
2Power
If P-type FinFET width is increased to match current drivability of N-type FinFET, then current drivability is equalized, but the area becomes three to four times larger
Solution Approach 1:
By stacking P-type FinFET vertically above N-type FinFET, the patent eliminates the need to increase P-type transistor width to achieve equal current drivability. The vertical arrangement allows both transistor types to maintain comparable widths while achieving equivalent performance, thereby reducing the overall layout area significantly
3Manufacturing precision
If ions are selectively implanted into source and drain of upper and lower transistors, then source and drain regions can be formed, but the process becomes complex and the lower device may be affected by ions for upper device
Solution Approach 1:
The patent introduces a buried oxide layer as an intermediary barrier between upper and lower FinFETs. This oxide layer prevents ion contamination from affecting the lower device during upper device fabrication, eliminating the need for complex selective ion implantation processes while maintaining manufacturing precision for source and drain region formation
Solution Approach 2:
The buried oxide layer is formed in advance before transistor fabrication begins. This preliminary action creates a protective barrier that simplifies subsequent processing steps, eliminating the need for complex ion implantation sequences and reducing overall process complexity
4Reliability
If contact hole of lower device is formed with exposed upper surface and interlayer dielectric layer on side surface, then electrical connection is achieved, but the process becomes complicated and difficult to implement
Solution Approach 1:
The buried oxide layer serves as an intermediary that simplifies contact hole formation. By providing a clear interface between upper and lower devices, it enables straightforward contact hole etching and filling processes without requiring complex exposure of upper surfaces or retention of interlayer dielectric layers on side surfaces, thereby maintaining electrical connection reliability while simplifying manufacturing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances circuit integration density by reducing layout area, increases current drivability, and simplifies the manufacturing process by eliminating the need for complex ion implantation, while maintaining high carrier mobility and electrical stability.
Implementation Method 1
defines source and drain regions through diffusion of the solid source material
Implementation Method 2
a buried oxide layer formed by Separation by IMplantation of OXygen (SIMOX)
Implementation Method 3
forms an upper device of an epitaxial layer of silicon or silicon germanium to increase carrier mobility
Data Source
AI summary
Provided are a dual structure FinFET and a method of fabricating the same. The FinFET includes: a lower device including a lower silicon layer formed on a substrate and a gate electrode vertically formed on the substrate; an upper device including an upper silicon layer formed on the lower device and the vertically formed gate electrode; and a first solid source material layer, a solid source material interlayer insulating layer, and a second solid source material layer sequentially formed between the lower silicon layer and the upper silicon layer. Therefore, the FinFET can be provided which enhances the density of integration of a circuit, suppresses thin film damages due to ion implantation using solid phase material layers, and has a stabilized characteristic by a simple and low-cost process. Also, mobility of an upper device can be improved to enhance current drivability of the upper device, isolation can be implemented through a buried oxide layer to reduce an effect due to a field oxide layer, and raised source and drain can be implemented to reduce serial resistance components of the source and drain to increase current drivability.