Vertical Thin-Film Transistor Memory Cells for High-Density Logic Integration
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Solution Overview
Problem
Current memory devices, such as DRAM, face challenges in achieving high density and bandwidth due to the spatial requirements of capacitors and limitations in scaling planar thin-film transistors, which hinder their integration with fast logic processing circuits.
Innovation Solution
The implementation of memory cells with vertical thin-film transistors (TFTs) reduces the area size of memory cells to 4F^2, allowing for high capacity and bandwidth, and by stacking these arrays, densities of 4F^2/N are achieved, where N is the number of stacked arrays, with shared sense amplifiers for efficient readout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If planar thin-film transistors are used in memory cells, then the transistor can be integrated with logic processing circuits, but the memory cell area becomes too large to achieve high density
Solution Approach 1:
The patent transitions from planar TFTs to vertically-oriented TFTs, changing the dimensional orientation of the transistor channel from horizontal to vertical. This allows the channel to extend through multiple metal layers in the vertical direction, achieving high density without increasing the planar footprint of the memory cell, while maintaining compatibility with back-end-of-line integration processes
2Area of moving object
If capacitor spatial requirements are reduced, then memory cell area decreases, but manufacturing precision and reliability become more challenging
Solution Approach 1:
The patent merges the capacitor structure with the vertical TFT channel by forming the capacitor plates using the same channel layer material and process steps. The capacitor first plate is formed from the channel layer itself, eliminating the need for separate capacitor fabrication processes and reducing manufacturing complexity while achieving compact integration
3Productivity
If memory cell area is reduced to 4F^2, then high density and bandwidth are achieved, but device complexity increases due to vertical stacking
Solution Approach 1:
The patent designs the vertical TFT structure to serve multiple functions: the channel layer forms both the transistor channel and the capacitor plate, the gate electrode serves as a reference for capacitor voltage, and the same vertical stacking approach can be used for both memory cells and sense amplifiers. This multi-functionality reduces overall device complexity despite the vertical stacking architecture
Data Source
AI summary
Embodiments herein describe techniques for a semiconductor device including a substrate oriented in a horizontal direction, and a memory cell including a transistor and a capacitor above the substrate. The transistor includes a gate electrode oriented in a vertical direction substantially orthogonal to the horizontal direction, and a channel layer oriented in the vertical direction, around the gate electrode and separated by a gate dielectric layer from the gate electrode. The capacitor is within an inter-level dielectric layer above the substrate. The capacitor includes a first plate coupled with a second portion of the channel layer of the transistor, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate of the capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.