Trench Gate IGBT Stray Capacitance Reduction
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Solution Overview
Problem
Semiconductor devices with trench gate IGBTs experience high switching loss and switching noise due to stray capacitance between trench gates and p-type floating regions, and inrush current through gate pads leads to resonance noise, which existing technologies fail to adequately address without compromising ON voltage and short-circuit resistance.
Innovation Solution
A semiconductor device design featuring a trench gate structure with an insulating film separating the trench gate from the p-type floating region, reducing capacitance and switching noise, and a lead out wiring system with higher resistance materials to restrict inrush current and prevent local switching of gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trench gates are electrically connected to p-type floating regions, then short-circuit resistance is improved, but stray capacitance increases causing higher switching loss
Solution Approach 1:
An insulating film is introduced as an intermediary between the trench gate and the p-type floating region. This mediator reduces the stray capacitance between these structures while still allowing the trench gate to be connected to the emitter region through the insulating film, thereby maintaining short-circuit resistance while reducing switching loss.
Solution Approach 2:
The connection path between the trench gate and the p-type floating region is segmented into two separate paths: one through the insulating film to the emitter region, and another through the semiconductor substrate to the floating region. This segmentation prevents direct capacitive coupling while maintaining electrical connectivity through controlled paths.
2Ease of operation
If voltage is applied to gate pad, then gate structure is activated, but inrush current flows through surface causing resonance noise and switching loss
Solution Approach 1:
Lead out wiring with higher resistance is introduced as an intermediary element between the gate pad and the gate structure. This mediator restricts the inrush current that would otherwise flow through the surface, preventing resonance noise while still allowing the gate to be activated when voltage is applied.
Solution Approach 2:
The resistance parameter of the lead out wiring is specifically increased compared to conventional gate metal wiring. This parameter change effectively restricts the inrush current and prevents surface current flow that causes resonance noise, while still permitting normal gate activation operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces switching loss and resonance noise while maintaining excellent ON voltage and short-circuit resistance by isolating trench gates from floating regions and controlling inrush currents, thereby improving overall device performance.
Implementation Method 1
there is a high amount of stray capacitance in the area connecting the respective trench gates and the p-type floating regions
Implementation Method 2
lead out wiring that is lead out from the pad section to the adjacent wiring section across the removal section, the lead out wiring being made of a material that has a higher resistance than the gate metal
Implementation Method 3
An LC resonant circuit is ordinarily formed by parasitic inductance and parasitic capacitance, so if surface current flows to the gate pad formed around the gate structure and the gate metal wiring lines, the switching of the gate structure will trigger resonance noise
Data Source
AI summary
A semiconductor device includes: an FET structure that is formed next to a looped trench on a semiconductor substrate and that has an n+ emitter region and an n− drain region facing each other in the depth direction of the looped trench across a p-type base region; a p-type floating region formed on the side of the looped trench opposite to the FET structure; and an emitter connecting part that is electrically connected to the n+ emitter region and a trench gate provided in the same trench, the emitter connecting part and the trench gate being insulated from each other by the looped trench. The trench gate faces the FET structure, and the emitter connecting part faces the p-type floating region, across an insulating film.