VFET Channel Length Control via Sacrificial Layer Recess
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Solution Overview
Problem
Current methods for forming vertical field effect transistors (VFETs) face challenges in controlling channel length due to factors like C/E non-uniformity, etch loading, and macro-to-macro variations, especially when using different work function metals for multiple threshold voltages.
Innovation Solution
A process flow is developed that involves forming a fin on a semiconductor substrate, creating a recess between sacrificial layers, depositing nitride and dielectric layers, and forming a gate electrode using work function metal, which allows precise control of the channel length and gate etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If recessing of gate dielectrics and metal gate is used to define channel length, then VFET structure is formed, but gate length variation occurs due to C/E non-uniformity, etch loading, and macro-to-macro variations
Solution Approach 1:
A sacrificial layer is introduced as an intermediary element between the gate dielectric recessing and the final gate formation. This sacrificial layer defines the channel length during fabrication and is subsequently removed, allowing precise gate length control without being affected by etch loading or C/E non-uniformity in the final gate structure.
Solution Approach 2:
The channel length is defined in advance during the gate dielectric recessing step using the sacrificial layer as a template. This preliminary definition of channel length occurs before the actual gate electrode formation, ensuring that subsequent gate processing steps do not affect the already-established channel dimensions.
2Adaptability or versatility
If different work function metals are used for multiple threshold voltages, then VFETs with different Vt are achieved, but gate length variation worsens
Solution Approach 1:
The gate structure is segmented into different work function metal layers deposited at different stages. By using the sacrificial layer to define channel length before any gate metal deposition, the patent enables sequential deposition of different WFM materials (e.g., TiN for NFET, TaN for PFET) without cross-contamination or interference, thus maintaining precise gate length control while achieving multiple threshold voltages.
3Productivity
If conventional gate formation methods are used, then VFET is fabricated, but high-k dielectrics are exposed to plasma which degrades them
Solution Approach 1:
The gate dielectric recessing and channel length definition are performed in advance using the sacrificial layer methodology, creating a protective configuration before high-k dielectric deposition. This preliminary structuring allows the high-k dielectric to be deposited and processed without subsequent plasma exposure that would degrade its properties, as the gate electrode formation occurs in a way that protects the dielectric interface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables efficient control of VFET channel length, reduces gate length variation, and protects high-k dielectrics like HfO2 from plasma exposure, making it suitable for mass production.
Implementation Method 1
A nitride material is deposited into the recess
Implementation Method 2
A dielectric layer is deposited on the nitride material and exposed portions of the fin
Implementation Method 3
A gate electrode is formed over sidewalls of the fin using a work function metal
Data Source
AI summary
Methods for making a vertical transistor and controlling channel length. A fin is formed over a semiconductor substrate. A bottom source/drain region is formed below the fin. A bottom spacer is formed above the source/drain region. A first sacrificial layer is formed around the fin. A second sacrificial layer is formed around the first sacrificial layer. A portion of the first sacrificial layer is removed to create a recess between sidewalls of the second sacrificial layer. A nitride material is deposited into the recess. The second sacrificial layer and remaining portions of the first sacrificial layer are removed. A dielectric layer is deposited on the nitride material and exposed portions of the fin. A gate electrode is formed over sidewalls of the fin.