Ferroelectric Non-Volatile Memory Reducing Gate Voltage
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Solution Overview
Problem
Non-volatile memory devices require high voltages for program and erase operations, which complicates manufacturing and increases costs due to the need for high-voltage components and processes.
Innovation Solution
Incorporating a ferroelectric material layer that achieves negative capacitance characteristics, allowing for increased internal voltage and reduced applied gate voltage, thereby enabling high-voltage operations without the need for high-voltage components and processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high voltage is applied for program and erase operations, then the memory device can perform write operations, but the device complexity and manufacturing cost increase due to requiring high-voltage components and processes
Solution Approach 1:
The patent changes the electrical parameters of the memory device by introducing a ferroelectric material layer that exhibits negative capacitance characteristics. This allows the device to generate high internal voltage (up to 11.5V) from a low applied gate voltage (2.5V), effectively transforming the voltage parameter relationship and eliminating the need for high-voltage external components and processes
Solution Approach 2:
The ferroelectric material layer acts as an intermediary between the control gate and the charge trapping layer. It amplifies the applied gate voltage through negative capacitance effects, generating the high internal voltage needed for program and erase operations without requiring high-voltage external circuitry. This intermediary layer enables voltage transformation while simplifying the overall device structure
2Power
If high voltage is used for program and erase operations, then data can be written to the memory device, but manufacturing costs increase due to high-voltage process requirements
Solution Approach 1:
The patent fundamentally changes the voltage parameter relationship by utilizing the ferroelectric material's negative capacitance property. The device achieves high internal operational voltage (11.5V) from a low applied gate voltage (2.5V), which simplifies manufacturing by eliminating the need for high-voltage process equipment and high-voltage component fabrication, thereby reducing manufacturing costs
3Power
If high applied gate voltage is applied, then high internal voltage is achieved, but device reliability decreases due to higher stress on components
Solution Approach 1:
The patent inverts the traditional voltage application approach. Instead of applying high voltage to the gate to achieve high internal voltage, it applies low gate voltage (2.5V) and uses the ferroelectric material's negative capacitance to generate high internal voltage (11.5V) internally. This inversion reduces stress on the gate and associated components, thereby improving device reliability while maintaining high operational voltage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the applied gate voltage while achieving high internal operational voltage, simplifies manufacturing by eliminating high-voltage components, and enhances device reliability and performance.
Implementation Method 1
the ferroelectric material layer of the non-volatile memory device is capable of achieving negative capacitance characteristics for effectively increasing the internal voltage for program/erase
Data Source
AI summary
A non-volatile memory device is provided. The non-volatile memory device includes a substrate, a first dielectric layer, a charge trapping layer, a ferroelectric material layer, and a gate layer. The first dielectric layer is disposed on the substrate, the charge trapping layer is disposed on the first dielectric layer, the ferroelectric material layer is disposed on the charge trapping layer, and the gate layer is disposed on the ferroelectric material layer.