Amorphous Silicon TFT Etching Process for Leakage Current Suppression

The patent segments the etching process into multiple distinct steps: first wet etching for the source layer, followed by first dry etching, second dry etching, and third dry etching for the amorphous silicon layer. This segmentation allows each etching step to be optimized independently, with wet etching providing rapid material removal and subsequent dry etching steps providing precise line width control to eliminate the bulging tail end problem.

The patent changes the etching parameters by switching between wet and dry etching methods, and between different dry etching conditions (inert gas plasma vs. nitrogen plasma). This parameter variation allows optimization of both etching speed and line width precision at different stages of the process, resolving the contradiction between productivity and manufacturing precision.

The patent segments the etching process into multiple steps with different photoresist thickness requirements. The first wet etching step uses a thick photoresist layer for complete coverage and protection, while subsequent dry etching steps use thinner photoresist layers that allow better line width control and precision, thus resolving the contradiction between coverage reliability and line width precision.

The thick photoresist layer is applied preliminarily to ensure complete coverage during the first wet etching step, establishing a reliable protective base. Subsequent thinner photoresist layers are then applied for precision work in later steps, allowing the system to benefit from both thick photoresist coverage and thin photoresist precision where needed.