Transistor TRIZ Cases

Vertical pillar-shaped bit line contacts expand the contact area to prevent mutual interference and reduce parasitic capacitance.

Vertical surrounding gate transistors eliminate well isolation and body terminals to reduce device area while maintaining transistor reliability.

Extending the source electrode as a light-shielding layer prevents negative threshold voltage drift and floating gate effects in metal oxide TFTs.

Segmented etching and photoresist baking suppress leakage current by eliminating amorphous silicon bulging tails that degrade display quality.

A ring-shaped conductive protection structure shields metal patterns from etching ions, preventing micro-trenching damage in thick insulation layers.

Single photolithography masks form N and P regions while the doped layer blocks unwanted crystal growth to reduce manufacturing complexity.

Layered oxide semiconductor films in active matrix substrates enable distinct threshold voltages and mobility levels for pixel and circuit transistors.

Angled local interconnects extend laterally between adjacent conductive structures to form self-aligned electrical connections within the device layer.

Threshold trigger circuit clamps voltage below breakdown level to prevent false triggering from parasitic capacitance in high voltage SCR ESD protection.

A ferroelectric dielectric blocking layer enables polarization switching to control the threshold voltage in non-volatile memory cells.

Patsnap Eureka TRIZ case shows preliminary CESL removal between gates reduces process complexity and cost while maintaining device reliability.

Dual source follower circuits in solid-state imaging devices reduce output signal line resistance and capacitance for faster pixel signal convergence.

An intermediary gate spacer suppresses hot-electron-induced punchthrough by blocking parasitic channels at the isolation boundary, reducing leakage current.

A thin-gate high-voltage switch uses segmented transistors and a pulse generator to reach 99% supply voltage within 500 nanoseconds.

A high selectivity etch stop layer arrests nitride etching during via formation, preventing overconsumption and reducing contact resistance.

Replacing silicon substrates with a composite thermal dielectric layer improves heat dissipation and breakdown voltage in high-power GaN devices.

Selective channel stress relaxation and biaxially compressive SiGe growth enhance carrier mobility in CMOS transistors.

A bistable switch injects gate charge via transformers to maintain stable ON states without continuous external voltage.

Trapezoidal strained source and drain structures concentrate stress on channel regions, resolving processing complexity while improving carrier mobility.

Graded doping in the gate electrode suppresses random telegraph signals and current leakage while maintaining low threshold voltage.

A plasma etching and deposition process forms a sidewall protection layer over mask structures during semiconductor fabrication.

Shared polysilicon films merge capacitor and transistor fabrication, reducing manufacturing steps while maintaining electrostatic discharge protection.

Deep trench isolation segments memory cells to enable forward-bias write operations, reducing power consumption during programming.

An intermediate layer blocks hydrogen and oxygen diffusion from the gate insulating film into the active layer during thermal treatment.

Crossed supporting layer patterns prevent lower electrode leaning and short-circuits during dense semiconductor capacitor manufacturing.

Current mirrors replicate emitter current to stabilize collector current, compensating for beta variations that degrade temperature measurement accuracy.

A TFT substrate scanning antenna uses a liquid crystal layer to steer beams by changing its dielectric constant.

Thermal conversion of a fluid precursor into silicon oxide eliminates voids in deep semiconductor trenches.

Segmented series-coupled diodes in a dual-well architecture reduce leakage current and capacitive loading while maintaining high ESD capability.

Overlapping capacitor arrangement increases aperture ratio while top gate transistors reduce photoresist mask count to lower production costs.

A MISFET structure applies a graded high dielectric constant gate insulating film to prevent sidewall contact degradation while reducing gate-drain capacitance.

Segmented drift and drain wells eliminate snapback effect and latch-up phenomena while maintaining high current handling capacity.

A high permittivity dielectric layer deposited on signal pads confines electric fields between adjacent chips to strengthen capacitive coupling.

Segmented SOI and bulk substrates enable defectless epitaxial growth, resolving dopant control issues in scaled CMOS finFETs.

Distributed latch-up suppression switches clamp power rails during transient electrical overstress events, preventing damage to sensitive mixed-signal circuits.

Stacked polysilicon and metal silicide layers in a vertical memory common source line reduce resistance while preventing interface peeling.

A dual-gate transistor structure stabilizes threshold voltage through back-channel control to reduce power consumption in semiconductor displays.

Segmented island-shaped wirings minimize plasma-induced charge accumulation, preventing electrostatic discharge damage to transistors and insulating layers.

Trench-based stacked electrodes boost capacitance per unit area, resolving signal attenuation issues in high-definition liquid crystal displays.

A substrate bias pump applies a steady state negative voltage to an NMOS back gate, reducing parasitic capacitance.

A phototransistor with a buried collector structure enhances low luminance sensitivity.

Drawing leads from lower pad ends reduces placement height, extending the display area within a narrow frame.

A light-transmissible electrode unit connects independent sensor lines to enable ambient and emitted light detection within a display panel.

Merging source, drain, and active layers reduces coupling capacitances and improves switching speed in X-ray detector thin film transistors.

Parallel diode-connected oxide thin film transistors shield signal lines from electrostatic discharge, reducing circuit complexity and manufacturing costs.

A polarity detector bypasses the internal body diode in a reverse conducting transistor circuit to enable low-loss switching.

Embedded Schottky diodes protect LDMOS transistors from electrostatic discharge damage without increasing on-state resistance.

Periodic clock signals control thin-film transistor switching to eliminate continuous current flow, reducing power consumption and fixed pattern noise.

Attaching an active layer to a light-shielding layer stabilizes voltage and eliminates extra masks, reducing manufacturing costs.

Integrating a bipolar transistor with a fusable element increases OTP memory density while maintaining CMOS manufacturing compatibility.