Vertical Memory Common Source Line Composite Layer Structure
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Solution Overview
Problem
The increasing demand for data processing in electronic devices requires higher integration of semiconductor memory devices, which existing technologies struggle to achieve with traditional planar transistor structures, particularly in terms of reliability and resistance issues in vertical memory devices.
Innovation Solution
The implementation of a memory device with a vertical structure featuring a common source line composed of multiple layers, including polysilicon doped with n-type impurities and metal or metal silicide layers, to enhance resistance and prevent peeling, thereby improving the device's reliability and integration capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-layer common source line is used in vertical memory devices, then the device structure is simpler, but resistance issues and peeling occur reducing reliability
Solution Approach 1:
The common source line is constructed using multiple layers of different materials: a first common source line layer made of polysilicon doped with n-type impurities, and a second common source line layer made of metal or metal silicide. This composite structure combines the advantages of polysilicon (good interface characteristics) and metal (low resistance) to simultaneously reduce resistance issues and prevent peeling, thereby improving device reliability without requiring overly complex structural modifications
2Productivity
If traditional planar transistor structure is used, then manufacturing is easier, but integration degree cannot be increased sufficiently
Solution Approach 1:
The patent transitions from traditional planar transistor structures to vertical transistor structures where channel areas extend in a direction perpendicular to the substrate surface. This dimensional change allows for increased integration density by utilizing the vertical space above the substrate, enabling higher capacity memory devices while maintaining compatibility with existing manufacturing processes through the use of stacked gate electrode layers
3Reliability
If polysilicon is used for common source line, then interface characteristics are good, but resistance is high
Solution Approach 1:
The patent creates a composite common source line structure where the first layer (polysilicon) provides good interface characteristics with the substrate and channel areas, while the second layer (metal or metal silicide) provides low resistance for efficient current flow. This layered composite approach allows both materials to contribute their respective advantages, simultaneously achieving good interface characteristics and low resistance without requiring a single material to satisfy both conflicting requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability and integration of semiconductor memory devices by reducing resistance issues and preventing peeling, allowing for more efficient data processing and storage in electronic devices.
Implementation Method 1
a first layer containing polysilicon doped with n-type impurities
Implementation Method 2
a second layer disposed on an upper surface of the first layer and containing at least one of a metal, a metal silicide, and a metal compound
Data Source
AI summary
A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of channel areas passing through the gate structure and extending in a direction perpendicular to the upper surface of the substrate, a source area disposed on the substrate to extend in a first direction and including impurities, and a common source line extending in the direction perpendicular to the upper surface of the substrate to be connected to the source area, and including a plurality of layers containing different materials.