Co-doped Gate Structure for Reducing RTS in Semiconductor Devices
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Solution Overview
Problem
Semiconductor manufacturers face challenges in reducing feature sizes and increasing device density while minimizing current leakage and random telegraph signal issues associated with buried channels in metal oxide semiconductor devices, which require modifications to the circuit design.
Innovation Solution
A semiconductor device with a buried channel and a co-doped gate, where the gate is doped with both n-type and p-type impurities, is fabricated using a method that allows for simultaneous mask usage across different MOS devices, reducing costs and maintaining low threshold voltage, low on-resistance, and high saturation current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a higher concentration and deeper depth of the buried channel is used to overcome random telegraph signal, then RTS is reduced, but current leakage increases and threshold voltage becomes uncontrollable
Solution Approach 1:
The patent changes the doping parameters of the gate electrode, specifically introducing a graded doping concentration where the doping concentration varies from the first end to the second end of the gate electrode. This parameter change allows the gate to exert more precise control over the buried channel, reducing current leakage while maintaining low threshold voltage, thus resolving the contradiction between reducing RTS and preventing current leakage.
Solution Approach 2:
The patent applies local quality by creating a non-uniform doping distribution in the gate electrode, where different regions of the gate have different doping concentrations. The first end of the gate electrode has a different doping concentration than the second end, allowing localized control over the electric field distribution and carrier concentration in the underlying semiconductor region, thereby controlling current leakage and threshold voltage independently.
2Reliability
If a higher concentration and deeper depth of the buried channel is used to overcome random telegraph signal, then RTS is reduced, but threshold voltage becomes uncontrollable
Solution Approach 1:
The patent introduces a graded doping concentration in the gate electrode, where the doping concentration transitions from the first end to the second end. This parameter change provides fine-tuned control over the threshold voltage by adjusting the doping profile, allowing precise control even when the buried channel concentration and depth are increased to reduce RTS.
Solution Approach 2:
By creating spatially varying doping concentration in the gate electrode, the patent enables localized control of the electric field and potential distribution. This local quality approach allows precise control of threshold voltage through the doping gradient, independent of the buried channel characteristics, thus resolving the contradiction between reducing RTS and maintaining threshold voltage control.
3Productivity
If feature sizes are decreased to comply with Moore's Law, then device density increases, but current leakage and random telegraph signal issues worsen
Solution Approach 1:
The patent employs parameter changes by implementing a graded doping concentration in the gate electrode, where the doping concentration varies along the length of the gate. This allows the device to maintain small feature sizes for high density while the doping gradient provides enhanced control over current leakage, compensating for the increased leakage tendency at smaller dimensions.
Solution Approach 2:
The patent applies local quality through the non-uniform doping distribution in the gate electrode, creating regions with different doping concentrations. This localized variation in doping quality enables precise control of current leakage in different regions of the device, allowing high device density with small features while suppressing current leakage through the doping gradient.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces random telegraph signals and current leakage while maintaining low threshold voltage and high saturation current, allowing for the fabrication of semiconductor devices with improved performance without significant changes to the original circuit design.
Implementation Method 1
the gate layer is doped with a fourth impurity and a fifth impurity to form a co-doped gate, in which the fourth impurity and the fifth impurity are mixed and distributed
Data Source
AI summary
The present disclosure provides a semiconductor device and a method of fabricating the semiconductor device. In some embodiments, the semiconductor device includes a substrate having a well region, a first source/drain region, a second source/drain region, a buried channel and a gate structure. The first source/drain region is located within the well region. The gate structure includes a co-doped gate including polysilicon and having a first concentration of a n-type impurity and a second concentration of a p-type impurity, in which the n-type impurity and the p-type impurity are mixed and distributed.