ESD Protection Circuit With Segmented Drift Well
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Solution Overview
Problem
Traditional LDMOS devices used for ESD protection in high voltage processes exhibit poor characteristics such as strong snapback effect and base push out, which degrade their ESD performance and render integrated circuits defective.
Innovation Solution
A compact ESD protection device is designed with a transistor having specific diffusion regions, device wells, and a unique configuration of drift and drain wells that prevent edges from extending below the gate, enhancing ESD performance and latch-up immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional LDMOS is used as ESD protection device in high voltage processes, then ESD protection function is provided, but strong snapback effect and base push out occur which degrade ESD performance
Solution Approach 1:
The device is segmented into multiple functional regions including a drift region with graded doping concentration, a drift well, and a drain well. This segmentation allows different regions to perform specialized functions: the drift region handles high voltage blocking, the drift well provides electric field control, and the drain well manages current distribution, collectively eliminating snapback effect while maintaining ESD protection
Solution Approach 2:
Different regions of the device are assigned different doping concentrations and structural properties. The drift region has graded doping concentration to optimize breakdown characteristics, while the drift well and drain well have specific doping profiles tailored for their respective functions. This local quality optimization eliminates harmful snapback effect while preserving ESD protection capability
2Power
If drift well edges extend below the gate, then current handling capacity increases, but latch-up phenomena occur
Solution Approach 1:
The drift well edges are deliberately positioned to not extend below the gate, creating a geometric constraint that prevents the formation of parasitic bipolar transistors. This preliminary structural design prevents latch-up phenomena before they can occur, while the drain well extends below the gate to maintain adequate current handling capacity
3Reliability
If compact ESD protection device is designed with specific well configuration, then latch-up immunity is enhanced, but device complexity increases
Solution Approach 1:
The drift well and drain well are merged into a single integrated structure with coordinated doping profiles. The drift well provides the upper portion with edges not extending below the gate for latch-up immunity, while the drain well extends below the gate for current handling. This merging reduces the number of separate fabrication steps and simplifies the overall device structure while maintaining enhanced latch-up immunity
Data Source
AI summary
A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region adjacent to the first side of the gate and a second diffusion region displaced away from the second side of the gate. The device includes a first device well which encompasses the device region and a second device well disposed within the first device well. The device further includes a drift well which encompasses the second diffusion region of which edges of the drift well do not extend below the gate and is away from a channel region, and a drain well which is disposed under the second diffusion region and extends below the gate.